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Cacheable RAM on a Socket 7 system

commodorejohn

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So I picked up a nice little Socket 7 PCI/ISA mobo with a Pentium 120 in it from liqmat's giveaway a while back, and I've finally gotten around to hooking it all up and getting a nice DOS/WfW setup going (tried Win95, but either it doesn't like the chipset or it's even crashier than I remembered...!) I'm enjoying having a play around with building a fairly maxed-out mid-'90s system after mostly sticking with 386 or earlier when doing DOS boxen in the past, but I'm a bit stumped on one particular aspect.

The board I'm using is a Chaintech 5SEM, based on the SiS 5511/5512/5513 chipset, and unfortunately the only documentation I can find anywhere online is a single-page jumper-guide PDF. Between that and the information silk-screened on the board, I've been able to determine that it supports a maximum of 1MB L2 cache, and I've lined up the appropriate bits for filling that out. However, what I don't know is what the maximum cacheable RAM is; it's nowhere in the jumper guide and not stated in the BIOS setup screen. posts on VOGONS and the like about similar boards indicate a limit of anywhere from 64MB to 256MB for 1MB cache, but this is only for similar boards from the same era; I can't find anything specifically relating to either this board or even just this chipset.

Is there a way to determine this without having the manufacturer's word for it, other than just popping in more and more RAM until it seems to take a speed hit?
 

commodorejohn

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Good idea, that - it took some doing to track down the datasheet for the chipset, but if the manufacturer is to be believed, 1MB of cache will actually support up to 256MB of cacheable RAM - which, amazingly enough, I can actually achieve since somehow or other I seem to have come into possession of a couple 128MB SIMMs I don't recall ever buying...

Though I have no idea what I'd actually use that much RAM for on a DOS box...

Edit: actually, though, upon closer review, this requires a separate 32Kx1 cache SRAM that my board doesn't have a socket for, so apparently 128MB is the maximum cacheable RAM for my purposes. Still plenty large enough, though...!
 
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commodorejohn

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It does, but since COASt (as far as I read) only supports up to 512KB cache anyway (and, as I read it, 512KB cache with 9-bit tag RAM is the same as 1MB cache with 8-bit tag RAM as far as cacheable RAM goes,) it doesn't sound like I'd be any better off tracking down the appropriate cache module than just filling the SRAM sockets.
 

Raven

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256MB is perfect for a 95 box if you plan on forcing it to run things it probably shouldn't be. :D

128MB is precisely the max limit for Win3x, so if you want to use that as the main OS that's kinda perfect.

Why would a system have both COAST and regular DIP cache available? For choice? What if you fill out both?
 

commodorejohn

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I don't think it'll recognize both; there's a DIP switch for cache type. My assumption is that the DIP sockets were provided for people who either A. wanted to swap over the cache chips from their old 386/486 board, or B. wanted the full 1MB of cache that as far as I can tell COASt modules never made it up to.
 

GiGaBiTe

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It wouldn't be a great idea to reuse old cache chips from a 386/486 on a Pentium because they'd be too slow. You'd need at least 15ns SRAMs for a 66 MHz bus where as 486 and older usually had 20/25ns or slower. 20ns would just work if you had a 50 Mhz bus Pentium.
 

commodorejohn

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Ah, I suppose. Anyway, if Wikipedia is correct that COASt modules only came in 256KB and 512KB sizes, they would've had to include the sockets anyway just to allow for 1MB cache RAM...
 

GiGaBiTe

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I went digging in old PC Magazine articles from the mid 90s and I found mention of a 1 MB COASt module, but could never find one in the products for sale lists. They may have existed, but probably were so expensive that hardly anyone bought them.

I have two COASt modules myself, one 256k and one 512k. I don't remember where the 256k module came from, but the 512k module came from my 1997 Gateway 2000. I did a benchmark in Quake and found the 512k module made the game around 12% faster. I wish I would have been able to test the 256k module as a comparison, but I didn't have it at the time.
 

GiGaBiTe

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The part numbers on those chips are illegible due to picture being size of postage stamp. Got any better HR pictures?
 

Syclops

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The part numbers on those chips are illegible due to picture being size of postage stamp. Got any better HR pictures?

The picture is 4000 X 3000 but the forum software is re-sizing it or something.

DSCF1607.JPG
 

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GiGaBiTe

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I changed the post above so it is linked directly to the image. Let me know if that is better.

Indeed, that is a much better picture. All of the chips except one, where the camera flash obscures it are legible now.

Not all of those chips are SRAMs, you have some DRAM mixed in there and one PAL.

MT4c4256-7 - Micron 256kbit FPM DRAM
TIBPAL16R6-15CN - Texas Instruments Programmable Logic Array
013-11-1BS - Some custom ACER chip (probably a GAL/PAL)
HY534256S-80 - 256kbit FPM DRAM
 

Syclops

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Indeed, that is a much better picture. All of the chips except one, where the camera flash obscures it are legible now.

Not all of those chips are SRAMs, you have some DRAM mixed in there and one PAL.

MT4c4256-7 - Micron 256kbit FPM DRAM
TIBPAL16R6-15CN - Texas Instruments Programmable Logic Array
013-11-1BS - Some custom ACER chip (probably a GAL/PAL)
HY534256S-80 - 256kbit FPM DRAM

OK thanks. Yeah it was just a bunch of random stuff I had laying around that I posted if someone knew what it was, and could use it, then all the better.
 

njroadfan

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Here are the specs from SiS


Supports Intel Pentium and Other Compatible CPU at 66/60/50 MHz (External Clock Speed)
Supports Shared Memory Architecture
Integrated Second Level (L2) Cache Controller
Supports Standard, Burst and Pipelined Burst SRAMs / Supports 64KB to 1 MB Cache Sizes
Integrated DRAM controller
Supports 4 Banks of SIMMs, the Memory Size is from 2MB to 512 MB
Supports 256K/512K/1M/2M/4M/16M x N70ns Fast Page Mode and EDO DRAM
Supports Symetrical and Asymmetrical DRAM
Table-free DRAM Configuration, Auto-detect DRAM Size, Bank Density, Single/Double Sided DRAM, EDO/FP DRAM for Each Bank
Supports Asychronous PCI Clock
Provides a 64/32-Bit Interface to DRAM Memory
Integrated ISA Bus Compatible Logic / Nuilt-in RTC with 256 Bytes CMOS SRAM
Built-in PCI Master/Slave IDE
Supports IDE PIO timing Mode 0, 1, 2, 3, 4 and Above of ANSI ATA Specification
Supports Multiword DMA Mode 0, 1, 2, and 3 / Two 8x32-Bit FIFO for PCI Burst Read/Write Transfers
On-Board Plug and Play Port

According to the datasheet, it can cache the following:

Cache Size
Data RAM
Tag RAM
Alter RAM
Cacheable Size

64K
8Kx8x8
2Kx8
2Kx1
16M

256K
32Kx8x8
8Kx8
8Kx1
64M

512K
64Kx8x8
16Kx8
16Kx1
128M

1M
128Kx8x8
32Kx8
32Kx1
256M

So 256MB is maximum cachable with 1MB installed. 128MB is maximum cachable with 512k installed.
 
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commodorejohn

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Yeah, but the key there is that 32Kx1 extra-tag-bit chip. If it doesn't have that (and my board has no socket for it,) the cacheable RAM is halved, so I'm limited to 128MB with 1MB cache.

Which, again, is way more than enough for DOS/WfW purposes. I was a little bummed that I couldn't max it out without making half the RAM uncacheable, but on the bright side my Amiga just made a fourfold jump in fast RAM capacity ;)
 
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