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Could it be possible to create a 65816 version of KIM-1?

J

jplr

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Hello,
There are excellent replicas of KIM-1 such as this one and amateurs are discussing such reproductions in forums like that forum.
There are 6502->65816 schematics (Daryl Rictor, Ruud Baltissen).
I am correct to think a Kicad schematics like the one from Eduardo Casino and adaptor schematics like the one from Ruud Baltissen, could make it easy to create a KIM-1 version using a 40 pins 65C816?

Thanks,
Jean-Pierre
 
But what do you want to achieve: A KIM-1 where the 6502 is replaced with a 65816 or something that looks like a KIM-1 but where the features of the 65816 are fully used? With the last I mean that it is capable of addressing more than 64 KB of RAM.
I imagine that you won't be satisfied with just 1 KB of RAM so it will be 8 or 32 KB. Why these numbers? this amount is available in the form of one IC. The next step would be 128 or 512 KB. Mainly an extra 74ALS573 is needed to be able to access the extra memory using a 65816.
Have fun :)
 
Thanks Rudd!

BTW I have been an avid reader of your website for many years!

You are right, I would prefer more memory. Yet in the early 1980' with 20kb and DACs, my SYM-1 was able to pilot 4 analog Moogs synthesizers with my own real-time kernel.
Plus it had software to compose musical partitions with a videotex terminal (French Minitel).
So somehow I know the futility of having 512kb memory if there is no OS, floppy and hard disks, etc.
I guess I could start with a KIM-1 with 65816.

Jean-Pierre
 
A 65816 KIM near-workalike already basically exists in a single chip. WDC sells an MCU called the W65C265S that’s a 65816 core combined with half a K of onboard RAM, a monitor ROM, and some I/O devices. (UARTs, tone generators, etc.) The chip has a programmable dual-purpose bus that allows either the use of external memory (with the full 24 bit bus already demultiplexed) or using the lines as additional parallel GPIO.

Considering how unobtainium the KIM’s RIOT chips are getting it seems like if you’re going to modify the design to really use a 65816 to anything like its full capacity you should probably update the I/O as well to use things currently available.
 
Thanks, Eudimorphodon (what a beautiful pseudo!)

> W65C265S
Actually, I have had a 40 DIP 65C816 for a few years and it sits in a drawer.

> Considering how unobtainium the KIM’s RIOT chips are
Yes, this is a considerable problem, I was naive. I/O chips like 6522, 6530, 6532 are not available anymore, except on eBay where we are not sure they are not fake.
I guess replacing the 6530 with a 6532 is a good alternative (I have Vince Briel's micro-KIM-1 where it's done).

I have a question: Could it be possible to use a microcontroller like the ATMEGA32-16PU to emulate those chips (6522, 6530, 6532)?
ATMEGA32-16PU has 32 I/O lines (only 16 are needed), it has two 8bits and one 16 bits timers (alas 6522 has two 16 bits timers), 1K or EEPROM and 2K of RAM (as well as flash memory) and it is available as 40 DIP package so from a distance they look legit. I guess the 6522 two 16 bits timers could be emulated by software. It is cheap.

Jean-Pierre
 
jplr said:
I/O chips like 6522, 6530, 6532 are not available anymore, except on eBay where we are not sure they are not fake.
Click to expand...

WDC makes a modern version of the 65C22 VIA, as well as the 65C21 PIA, and both are readily available. (Unless there's some kind of supply chain backup going on... nah. Mouser has them in stock., at least) Even leaving them out there are ample supplies of old-stock VIAs and PIAs out there compared to the 6530/32.

Using the ATMEGA to emulate one of these chips isn't a really great prospect unless you want to redesign the system so the ATMEGA controls the system clock and can halt/cycle stretch the CPU whenever it needs to. They're just not fast enough to react in real time to external requests like that. A Raspberry Pi Pico might be able to do it, but there really isn't a lot of point.
 
Thanks, I did search for 6522 on Mouser but couldn't locate it so I deduced it was not available anymore (I didn't think of WDC, I am still stuck in the 1980' :-(.
I guess it will be a PCB without 6530/6532.
 
One of the problems that I encounter when interfacing modern MCUs with older logic is that the MCU is often too fast. Take my favorite STM32F4 chips--168MHz basic CPU clock, with the GPIOs running at 84MHz. If that can't keep up with a 1MHz-clocked 6502, I'm a monkey's uncle.

Of course, the straighforward thing would be to simply have an MCU emulate the KIM/SYM and forget about everything else. But that's just me. :)
 
> straighforward thing would be to simply have an MCU emulate the KIM/SYM

For me it's about nostalgia, as a lot of people I spent an incredible amount of time on my SYM-1 when I was young, so having a PCB of the same size and similar look would be enough. I have already Vince Briel's Micro-Kim which is a very nice object, but somehow its PCB is too small to evoke the look and feel of the SYM-1.
I still recall the day I take it at home, attached a quick and dirty PSU, and programmed a 1khz sound on the speaker. This little PCB transformed my life.
If there is no 6530/6532 I don't care, as long as there are 6522s :)
 
Chuck(G) said:
One of the problems that I encounter when interfacing modern MCUs with older logic is that the MCU is often too fast. Take my favorite STM32F4 chips--168MHz basic CPU clock, with the GPIOs running at 84MHz. If that can't keep up with a 1MHz-clocked 6502, I'm a monkey's uncle.
Click to expand...

I think the issue isn't so much raw speed (although that would be a thing with a 16mhz single-threaded Atmel) as latency/asynchronous timing. The 65xx/68xx 8-bits in particular have pretty unforgiving bus timing that expects perfectly synchronous behavior from peripheral chips. (IE, it's significantly harder than some other CPUs to just slap in arbitrary wait states.) The Raspberry Pi Pico has dedicated state machine and DMA hardware to accelerate GPIO transactions so it's "pretty easy" for it to keep up with a 1mhz 6502 (people have managed to, for instance, create an Apple II "VGA card" that works via bus snooping), and I think I've seen similar feats from STM32 chips, but you still need to throw a fair amount of muscle at it to make work.

(Being a slave device on an 8-bit parallel bus is where some PIC and Intel 804x-family MCUs really shine, since they specifically offer bus modes to make them "look like" an I/O chip.)
 
The STM32F4 series have multiple DMA controllers that can run at full speed. If that's not fast enough, try an STM32H7.
Honestly, in at least two of my designs, I have a subroutine coded to delay a certain number of 500 nsec units. It does so quite accurately. CMOS has come a long way in 50 years.
 
jplr said:
If there is no 6530/6532 I don't care, as long as there are 6522s :)
Click to expand...
That's the spirit! When using a 65816 and having the intention to use its extra features, you will end up with a ROM that will be different from the original one anyway. Just try to change the original code in such a way that the original entrances to the various subroutines are kept. (original) Programs that run on a real KIM and, for example, want to read a key, will call the according routine at $WXYZ. That your routine uses a 6522 instead of the original 6530 to read that key won't matter then. What matters is that it outputs that what the calling routine expects to receive.
Using 6522s will have a disadvantage: programs that address the 6530 won't work because the I/O part is completely different.

Please keep us informed!
 
I tried to sketch what the processor section of Eduardo Casino's KIM-1 schematics might be when if it used a 40 DIP 65c816.
- There is a latch on the data bus for the upper section of the address bus (A16-A23).
- There is a buffer on the data bus
- I left the clock circuitry as it was, except there is not any more Phi2 connection to the quartz.
- VPA/VDA are fully decoded
- All signals such as RDY, BE, MX, etc are connected to an extension bus specific to signals.
- Phi 1 is not used any more.
Indeed I am deeply indebted to many people...
Please be kind, for the last 38 years I never dealt with hardware!
How many obvious errors are there?
1687462886900.png
 
Be aware that the way you use READY won't work in this way. The moment you negate RDY, the 65816 won't supply the address lines A16..23 anymore and your 573 latch will clock what is on the data bus at that moment. Please have a look at this page where all will be explained and a solution is given as well.
 
> The idea is simple: the moment CLK=(H) and RDY=(L), CLK0 will be kept (H) until both CLK and RDY are (H) again.

So if I understand correctly, you synchronize RDY on Phi 1?
1687549378201.png
 
No. The moment I want to stop the 65816, I keep its clock, PHI0, High. The clock for the latch is noting more than the inverted PHI0. Hmmm, I only see now that the text says CLK0 and the picture PH0. Have to correct that later. CLK1/PHI1 that goes to the rest of the computer just keeps on ticking.
 
I had a stupid idea and I want to share it, sorry for that.
What I liked in 6502 (like in LSI-11) was the variety of address modes.
This post may carry highly erroneous statements, I go back to the 65xx family after nearly 40 years of errance on unrelated topics.

On NMOS 6502 there are a number (14?) of 16 bits addressing modes.
- Absolute
- Absolute Indexed with X
- Absolute Indexed with Y
- Absolute Indirect JMP

On 65c02 there is in addition:
- Absolute Indexed Indirect

The 65c816 adds 24 bits addressing modes including:
- Absolute Long
- Absolute Long Indexed with X (X may be 16bits)
- Absolute Indirect Long

So for symmetry's sake the 65c816 is missing:
- Absolute Long Indexed with Y (X may be 16bits)

=> 1. What if a bit mode would enable this Absolute Long Indexed with Y ?

If we look at page zero addressing we can make a similar observation:
The 65c816 adds Zero page addressing modes in first 64K addresses.

=> 2. What if a bit mode would enable Zero page addressing modes in 16M addresses?
=> 3. What if a bit mode would enable Direct Page Indexed long Indirect with X (Preindexed)

On NMOS 6502:
- Zero Page
- Zero Page Indexed with X
- Zero Page Indexed with Y
- Zero Page Indirect Indexed with Y (Postindexed)
- Zero Page Indexed Indirect with X (Preindexed)

On 65c02 there is in addition:
- Zero Page Indirect

The 65c816 adds these addressing modes:
- Direct Page Indirect Long
- Direct Page Indirect Long Indexed with Y

So for symmetry's sake the 65c816 is missing:
- Direct Page Indexed long Indirect with X (Preindexed)

* I think the point 1. is feasible with a simple proposal similar in principle to LAUGHTON ELECTRONICS' KimKlone
When a mode bit would enable it, the "Absolute Indexed with Y" becomes "Absolute Long Indexed with Y"
In memory there is:
- Operation code
- AD0-AD7
- AD8-AD15
- AD16-AD24

The 65c816 would "see"
- Operation code
- AD0-AD7
- AD8-AD15
- NOP

1688159275816.png

An external circuitry would:
- decode the Fetch cycle (with VPA/VPB)
- store AD16-AD24 in a buffer
- When the read or write cycle would happen, the AD16-AD24 value from this buffer would be used as AD16-AD24.

* I think the point 2. (enable Zero page addressing modes in 16M addresses) is feasible with this proposal:
- decode the Fetch cycle (with VPA/VPB)
- When the read or write cycle would happen, the AD16-AD24 value comes from a 8 bits buffer and would be used as AD16-AD24. There could be multiple (many) such buffers.
- Alternatively, When the read or write cycle would happen, the AD8-AD24 value comes from a 16 bits buffer and would be used as AD8-AD24.

* I think the point 3. (Direct Page Indexed long Indirect with X) is feasible with this proposal:
- decode the Fetch cycle (with VPA/VPB)
- When the read or write cycle would happen, the AD16-AD24 value from a buffer would be used as AD8-AD24. There could be multiple (many) such buffers.

Is this absolutely useless or are some bits may be valuable?

Jean-Pierre
 
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