• Please review our updated Terms and Rules here

Cromemco dazzler replica project

It is there on the schematic - that is how I spotted it in the first place...

Can you also check IC62 pins 1 and 16 please. Both of these should be connected (via a similar bit of 'magic copper') to 0V. If this is not there - this could well be messing up our DMA address (again, not that it will make any difference to your problem in the short term, but it will in the longer term). It could also indicate a more wide-spread issue that we may need to address...

Dave
 
HOWEVER, I would not 'short it out' until a few other people have had a look and voiced their opinions. Shorting something to the +5V rail is quite drastic. Myself, I would probably pull it to +5V using a 1k resistor.

Ok so I hooked it up with a 1K resistor as you recommended. Everything seems to be functioning the same as before, no color though in GDEMO as you thought.
 
At least it should read a much better voltage now though (less noise susceptibility as well).

This design 'skimped' on decoupling capacitors. As a result, you can see noise all over the place...

Did you read my post #582?

This is why it is important to enter the schematics as well as the PCB layout. The Design Rules Checker (DRC) can then test for stupidities - i.e. PCB tracks where there are none on the schematic and missing PCB tracks where they should be present. In order for a fault to 'sneak through' you would have to make an identical mistake on both the schematic and the PCB layout.

Dave
 
Can you also check IC62 pins 1 and 16 please. Both of these should be connected (via a similar bit of 'magic copper') to 0V. If this is not there - this could well be messing up our DMA address (again, not that it will make any difference to your problem in the short term, but it will in the longer term). It could also indicate a more wide-spread issue that we may need to address...
Yep just checked the board, IC62 pin 1 has a small trace to up to the GND rail (as does 3 & 8).
 
After that, we will be looking at the A, B, C and D outputs from ICs 32 and 33.

When the /L pin is LOW, the outputs should be preset to ABCD = 1000.

When the /L pin is HIGH, IC 32 and 33 should count up from the initial value of 1000. The carry from IC 33 should count +1 into IC 32.
Ok so back to this test and now that I'm looking at the correct (output) channels:

IC32 A = 111 KHz
IC32 B = 64 KHz
IC32 C = 32 KHz
IC32 D = 16 KHz

IC33 A = 1.79 MHz
IC33 B = 896 KHz
IC33 C = 448 KHz
IC33 D = 224 KHz

D5 = 1/0 doesn't seem to impact any of these pins.
 
>>> D5 = 1/0 doesn't seem to impact any of these pins.

Correct.

IC32 and IC33 are the fundamental counters for the state machine.

Did you see the bit about triggering the oscilloscope on /L and working your way forward through the logic?

Check the inputs to the simple gates and work out what the output should be (from the AND or OR truth table) and see if that is what you get on the output of the gate you are checking.

At some point, we must find some missing pulses that should be there...

Dave
 
>>> D5 = 1/0 doesn't seem to impact any of these pins.

Correct.

IC32 and IC33 are the fundamental counters for the state machine.

Did you see the bit about triggering the oscilloscope on /L and working your way forward through the logic?

Check the inputs to the simple gates and work out what the output should be (from the AND or OR truth table) and see if that is what you get on the output of the gate you are checking.

At some point, we must find some missing pulses that should be there...

Dave

I did see this but am not very clear on the test procedure. These gates you're referring to are IC's 8, 20, 21, 22 and 30 - correct? Guess it's time I learned how to read/interpret these truth tables anyways! :D I'll see what I can do.
 
I did see this but am not very clear on the test procedure. These gates you're referring to are IC's 8, 20, 21, 22 and 30 - correct? Guess it's time I learned how to read/interpret these truth tables anyways! :D I'll see what I can do.
Yep.

For an AND gate, all of the inputs have to be HIGH for the output to be HIGH. All other input combination results in a LOW output.

For an OR gate, all of the inputs have to be LOW for the output to be LOW. All other input combinations results in a HIGH output.

For a NAND gate, the output is the inverse of an AND gate.

There you are, that is all you need...

I suppose you did try these by substitution of the IC packages anyhow?

Dave
 
Last edited:
IC8 pin 6 is fundamental to the operation of the DMA circuit. It requests the S-100 bus, holds up the Z80 processor and transfers the data into the circular shift register for one line.

Each 'pulse' corresponds to fetching one (1) byte of data from main memory and into the circular shift register.

IC8 pin 6 is active LOW - so you can get output pulses by pulling either input pins 4 or 5 low. So here would be the first place to look. Keep your oscilloscope trigger on the "T" point at 5 us/div as per the test procedure.

Dave
 
The IC33 pin 10 short link to +5V is another case where a pullup link was missing. (most likely the for the same reason as the other example) but it doesn't stop the dazzler from working. No doubt both these happened because of the very poor foil patterns I was working with. Like the other case, best to simply link it as Cromemco did to +5V.
 
The extra pulses (when D5 is operated) are introduced by IC21 pins 11, 12 and 13.

IC21 pin 12 is directly controlled by D5.

Dave
 
One thing that helps figuring out what the gates do, in some particular circuit, is to think of them on their DeMorgan equivalent, if the signals are active low. In many cases designers draw them in this form to help explain what they are trying to do.

For example a NAND gate behaves as an a OR gate where its inputs are negated (inverted) so that you get a high output when either input is low.

A NOR gate, behaves as an AND gate with negated inputs, so both inputs have to be low to get a high output.

If you imagine the OR gate in its negative logic form, it is a negative logic AND gate with a negated inputs and output, so it can be drawn as an AND gate with small circles on its three terminals. So, both its inputs have to be low to get the low output.

I have attached a couple of useful charts, including XOR. As noted on this chart, the Pong game had a very unusual version of the XOR, until I figured out that was an XOR, it was quite a tricky one to wrap the head around.
 

Attachments

  • gates.jpg
    gates.jpg
    170.3 KB · Views: 1
Last edited:
Unfortunately I have 6 poodles who are in desperate need of some grooming, so that will probably be taking most of my free-time attention for the next couple of days. Will post an update when I can.
 
Last edited:
This is why it is important to enter the schematics as well as the PCB layout. The Design Rules Checker (DRC) can then test for stupidities - i.e. PCB tracks where there are none on the schematic and missing PCB tracks where they should be present. In order for a fault to 'sneak through' you would have to make an identical mistake on both the schematic and the PCB layout.

Dave

Yes, but that would have made the job many times more difficult.
 
Yes, always the trade off...

Is it better for one person to put in the effort upfront or to debug the resulting PCB later?

Dave
 
It would probably help if @Hugo Holden could probe IC8 pin 6 for us with his oscilloscope and post what he is observing.

Perhaps by setting Dazzler port 0Eh to 80h and port 0Fh to 59h (x4 resolution, 512B memory, colour, high brightness RED) and then 19h (x1 resolution, 512B memory, colour).

After you have sorted out the poodles, I have worked out how the colour DAC works, so we can do a few simple checks with the oscilloscope for a bit of light relief from the system controller logic.

Dave
 
US patent 4121283 makes the circuitry 'obvious'...


Download the PDF.

Dave
 
It would probably help if @Hugo Holden could probe IC8 pin 6 for us with his oscilloscope and post what he is observing.

Perhaps by setting Dazzler port 0Eh to 80h and port 0Fh to 59h (x4 resolution, 512B memory, colour, high brightness RED) and then 19h (x1 resolution, 512B memory, colour).

After you have sorted out the poodles, I have worked out how the colour DAC works, so we can do a few simple checks with the oscilloscope for a bit of light relief from the system controller logic.

Dave
Currently my Sol is in a storage location to make space for other antics on my bench and the Dazzler boards not fitted.

That patent document is an interesting find, it confirms what I had thought about this circuit, it is creative & interesting. But the trouble with patents, as my patent lawyer remarked, a patent generally is a legal document, not a technical one and a lot of the time they are significantly modified by the lawyers (both the diagrams and text) to cover all manner of contingencies that are unrelated to the function of the device in its simplest form, which is of course the form that the engineer wants it described in.
 
Last edited:
nullvalue, your requested IC's are being picked up today by the USPO and should take 4-5 days for delivery (plus any delayed caused by the holiday) All are 1980's or earlier date codes and picked for that reason. I included a couple of extra 7404's because I had a bunch of them. Between the guys with knowledge and perhaps some old dated parts I'm sure you'll have the board running soon.
 
Back
Top