Back on topic, here’s an idea for a really minimal decoder that’s even simpler than my first idea but gives you the basis for an easy to use expansion bus system:
Forget about using LCS and the MCS lines, the only one we care about is UCS, which is the chip select for the ROM subsystem. Like before we set up a 1MB RAM array, and the select for said array (active low) is connected to a multi-input NAND gate, which has pull-up resistors on all inputs except one, which is connected to UCS. (Along with the ROM array, obviously.)
The result of this setup is RAM will be selected whenever ROM isn’t. The exact mapping will automatically adjust based on the block size set for UCS; at power-on you’ll have 1023K of RAM and 1K of ROM, but if you set the block size for UCS to, say, 64K, you’ll automatically remap to 960k of RAM/64K ROM No fuss, no muss.
Beauty of this system: Remember the other input(s) on the NAND gate we used instead of an inverter? If you add memory-mapped peripherals (video or whatever) all you need to do is decode them wherever you want under the bottom of ROM and have their memory selects pull an input on that gate whenever memory on the peripheral is active. This lets you create “memory holes” at any location you want, up to and including substituting paged memory for the wired memory after the fact. (Some might recognize this idea as inspired by the *Phantom line on the S-100 bus.)
This peripheral override could be implemented either as a separate override input for each ‘slot’ (using a 7430 8-input NAND would give you seven overrides on top of the one connected to UCS), or you could have a common line with a more powerful pull-up and use open collectors on the peripheral decoders to pull it down.
