Looking for a datasheet DEC T11 Cpu

[GilesGoat]

Ok let's see if I can make your mood a bit better with this

FIRST OF ALL, I am *STILL* working on all this is UNFINISHED, UNTESTED, ETC.

So this IDE .. really challenging .. it would be "really easy" if RAS + address would be enough to understand what's going on, but it is not because you have to consider CAS into the equation, there could be CAS with no RAS ( ASPI ) and other stuff ..

However .. after much studying of this & that I come with this idea ..

The idea is to have "something" to generate the IDE /CS0 signal which goes '0' when CAS goes '0' and returns '1' when RAS goes '1' ( IDE /CS1 will be always at 1, nobody uses it ) .

At this point if I understood correctly PI goes '0' about 10ns after CAS goes '1' ( so CAS returns to '1' before PI does ).

Also, other important thing, if I read correctly between CAS going '1' and RAS going '1' too there are 10 ns of time.

Now to understand what I've done you have to compare those two things, this diagram :

With the one of the datasheet Figure A-2 page A-24

With the following VHDL ( which I repeat is still totally uncompleted and UNtested and such )

It synthesize anyway more or less as I tought it should have been.

I *THINK* doing this way it should all fit within "mode 6" but between this and "it works" I don't know yet.

The rest, has still to come.

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:50:53 04/10/2011 
-- Design Name: 
-- Module Name:    Main - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Main is
    Port ( DAL : inout  STD_LOGIC_VECTOR (15 downto 13);
           ready : out  STD_LOGIC;
           bclr : in  STD_LOGIC;
           pup : in  STD_LOGIC;
           sel : in  STD_LOGIC_VECTOR (1 downto 0);
           pi : in  STD_LOGIC;
           x1_clock : in  STD_LOGIC; -- 10 Mhz clock from the oscillator
           cpu_clock : in  STD_LOGIC; -- cpu clock "microcycle" style
           negRas : in  STD_LOGIC;
           negCas : in  STD_LOGIC;
           rNegWLB : in  STD_LOGIC;
           rNegWHB : in  STD_LOGIC;
           AI : in  STD_LOGIC_VECTOR (4 downto 1);
           dal11 : inout  STD_LOGIC;
           dal8 : inout  STD_LOGIC;
			  dal2 : inout  STD_LOGIC;
           dal1 : inout  STD_LOGIC;
           ADLatch : out  STD_LOGIC;
           romOE : out  STD_LOGIC;
           ramWEH : out  STD_LOGIC;
           ramOEH : out  STD_LOGIC;
           ramWEL : out  STD_LOGIC;
           ramOEL : out  STD_LOGIC;
           IDE_AD : in  STD_LOGIC_VECTOR (2 downto 0);
           IDE_CS0 : out  STD_LOGIC;
           IDE_WR : out  STD_LOGIC;
           IDE_RD : out  STD_LOGIC;
           SPI_SS : out  STD_LOGIC;
           SPI_MISO : in  STD_LOGIC;
           SPI_MOSI : out  STD_LOGIC;
           SPI_CLK : out  STD_LOGIC);
end Main;

architecture Behavioral of Main is

-- for coherence with the T11 architecture we'll use the OCTAL notation

signal l_add : STD_LOGIC;

signal rom_sel : STD_LOGIC; -- when active at '0' means ROM address space is selected
signal io_sel : STD_LOGIC; -- when active at '0' means I/O address space is selected
signal ram_sel : STD_LOGIC; -- when active at '0' means RAM is selected
signal mode_read : STD_LOGIC; -- when active at '0' means the CPU is reading the MODE register
signal word_read : STD_LOGIC; -- when '0' means both lines rNegWLB,rNegWHB are at '1'
signal word_write : STD_LOGIC; -- when '0' means both lines rNegWLB,rNegWHB are at '0'

signal negPi : STD_LOGIC; -- not PI used for the IDE cycle
signal ideEnable : STD_LOGIC;
signal ide_read : STD_LOGIC;
signal ide_write : STD_LOGIC;
signal ide_inuse : STD_LOGIC;

signal MAD : STD_LOGIC_VECTOR (15 downto 11);



begin


l_add <= NOT ( negRas ); -- trivial, just to latch the addresses with those 574
ADLatch <= l_add;

-- let's not forget the CPLD too has RAISING EDGE sensitive FFs
LATCH_ADDR: process ( l_add )
				begin
				 if ( l_add'event and l_add='1') then
				    MAD <= DAL(15 downto 13)&dal2&dal1;
				 end if;
				end process;

-- we add the condition of the mode_read as well so to avoid I/O or mem selected
-- while the CPU is reading the mode register

io_sel <= '0' when MAD(15 downto 13) = "111" and mode_read = '1' else '1'; -- last 8K of address space is I/O, 160000 - 177777
rom_sel <= '0' when MAD(15 downto 13) = "110" and mode_read = '1' else '1'; -- 140000 - 157777 ROM
ram_sel <= '0' when io_sel = '1' and rom_sel = '1' and mode_read = '1'; -- anything else is RAM

-- with the selection above there's only one choice for the mode register

mode_read <= ( pup OR bclr ); -- it has to be a PUP low and BCLR low 

-- restart address at 140000, 16 bits bus, normal R/W, constant clock nah bananez

DAL <= "000" when mode_read = '0' else "ZZZ";
dal11 <= '0' when mode_read = '0' else 'Z';
dal8 <= '0' when mode_read = '0' else 'Z';
--dal0 <= '0' when mode_read = '0' else "Z"; let's leave the other clock

-- ROM output enable, just as a paranoia we could include word_read

word_read <= NOT ( rNegWLB AND rNegWHB ); -- no write to ROM allowed
romOE <= '0' when rom_sel = '0' and word_read = '0' and negCas = '0' else '1'; -- plain and simple

-- RAM, just lightly more complex but nothing too weird here
-- this fundamentally means that he "ram cycle" is the duration of negCAS only because it HAS
-- to be the condition RAS = '0' AND CAS = '0' for a valid access, SEL lines are of no help

ramOEH <= '0' when ram_sel = '0' and rNegWHB = '1' and negCas = '0' else '1';
ramWEH <= '0' when ram_sel = '0' and rNegWHB = '0' and negCas = '0' else '1';

ramOEL <= '0' when ram_sel = '0' and rNegWLB = '1' and negCas = '0' else '1';
ramWEL <= '0' when ram_sel = '0' and rNegWLB = '0' and negCas = '0' else '1';

-- IDE stuff, let's see if it gets somewhere

negPi <= NOT ( pi );

-- this is a D type flip flop with preset and clear and an '1' stuck into 'd'
PR_CS0 : process ( bclr, negCas, negRas )
		    begin
			  if bclr = '0' then ideEnable <= '1'; -- '1' at reset
			   elsif negCas = '0' then ideEnable <= '0'; -- '0' when CAS = '0'
			   elsif negRas'event and negRas = '1' then ideEnable <= '1'; -- '1' at the rising edge of RAS
			  end if;
			end process;

word_write <= rNegWLB OR rNegWHB;
			
ide_read <= io_sel or MAD(12) or MAD (11) or word_read;
ide_write <= io_sel or MAD(12) or NOT MAD (11) or word_write;

ide_inuse <= ide_read and ide_write; -- '0' when some I/O is in the ide

-- and there is the magic

IDE_CS0 <= ideEnable or negRas or ide_inuse;
IDE_WR <= ideEnable or negPi or ide_write or negCas;
IDE_RD <= ideEnable or negPi or ide_read or negCas;


end Behavioral;

Note : if I've done something completely crap it could well be, my mind is still grinding over all this ..

[edit] - it's that 't9' that I don't quite like much, I am thinking instead of using RAS for that to use a signal where I make RAS pass throught a couple of gates or stuff trying to delay it for 5 .. 10 ns more, that should be better, it could give me 20 ns of time extra I may need.

 

[RSX11M+]

Before I can answer, I need to know more exactly the MODE you intend to run the T-11 in.

Obviously this must match your design. Are you designing for:

• 16 bit bus, MR [MODE Register] bit <11> = 0
• "Static" bus [no DRAM], MR bit <9> =1
• Normal or Delayed Read / Write, MR <8> = ?
• Have you decided on COUT, MR <0> = ?
• Long or Standard Microcycle, MR <1> = ?

Depending on these answers, my response to the use of RAS or CAS would be quite different.

 

[GilesGoat]

Before I can answer, I need to know more exactly the MODE you intend to run the T-11 in.

Obviously this must match your design. Are you designing for:

• 16 bit bus, MR [MODE Register] bit <11> = 0
• "Static" bus [no DRAM], MR bit <9> =1
• Normal or Delayed Read / Write, MR <8> = ?
• Have you decided on COUT, MR <0> = ?
• Long or Standard Microcycle, MR <1> = ?

Depending on these answers, my response to the use of RAS or CAS would be quite different.

Right ..

16 bits bus
STATIC mode
NORMAL write
STANDARD microcycle
COUT I think I could use "cpu mode" ( i.e. clock every microcycle ) this could allow me to use a combination of the "in clock" ( 10 mhz ) and that for various things.

Also, if I understood correctly when you have "Delayed" it means the timing or RW... is identical to the one of CAS right ?

 

[RSX11M+]

I think in your case then,

ADDRESS LATCH Behavior:

I would use -RAS to Latch the ADDRESS into the address line drivers [on the falling edge], and enable the output of same to the memory devices and decoders.
​

MEMORY READ:

I would choose to generate a -READ, valid from the falling edge of -CAS and negate it on the rising edge of -RAS. It would be true only when -WLB and -WHB are negated. This would be conducted to the -OE lines on static ROMs and RAMs.
​

MEMORY WRITE:

I must say that I question your decision to use "Normal" [MR bit <8> = 0] rather than "Delayed" Writes. If you stay with the mode you've selected, I would make new -WRL and -WRH signals [from -CAS and -WLB and -WHB] and use these to drive -WR lines of static RAMs, ROMs and word I/O.
​

DEVICE ENABLES:

Device ENABLES would be driven by address decoders enabled during assertion of -RAS.
​

BYTE I/O READ / WRITE:

-READ would be combined with A0 in an attempt to differentiate BYTE reads from WORD reads and used to make -BRD. The T-11 is a "High Byte in High Memory" machine, so when A0=1 the "High byte" data is taken from DAL<15-8>.

Similarly -WRL would be combined with A0 to create -BWR.

Then I would also choose to assign all 8-bit I/O registers at ODD addresses only, in effect enabling them only when A0 was high.

All 8-bit I/O devices that contain volatile data, [reset when read] would be accessed only using -BRD and -BWR to prevent unintended reads during WORD READ / WRITES from effecting them.

This practice ensures BYTE I/O can only be accessed using BYTE INSTRUCTIONS.
​

I/O ARCHITECTURE WARNING:

When Defining any I/O register placement [BYTE or WORD], be sure not to "overlay" multiple registers at the same address ( I.E. Control [Write] with Status [Read] ) to avoid complications from the CPU's involuntary READ-before-WRITE action. Otherwise, this would cause loss of Data which resets-on-read such as "RX Data Available" flags, or "RX Data" when ever writes occur.
​

 

[GilesGoat]

Ok then

Has to be remembered that "RAS alone is not enough" because only a condition where both RAS and CAS are '0' means there is really a read/write cycle.

ADDRESS LATCH : in fact, I use a NOT ( RAS ) only because my latches are positive edge sensitive and not, transparent latches could be used as well.

MEMORY READ : in fact I use CAS ORed with RAS for that. That I use it in combination with R-WHB and R-WLB in fact but then I would be also better to include A0 into it to know which portion of the bus is being used.

MEMORY WRITE : my signal in fact always combines CAS into it. Let's not forget you could have a cycle where RAS is HIGH and CAS is low ( ASPI ) a valid memory read/write cycle must have RAS and CAS low the same time.

DEVICE ENABLES : in fact, that's precisely what I do, I decode adresses latched on the falling edge of RAS ( raising edge of NEGATED RAS in my case )

BYTE I/O read/write, I'll modify a bit that so to generate proper signals, byte write is "easy" becase WHB and WLB do, for "read" I see you have to use A0 to generate let's say an RHB and RLB

I/O architecture : yes I got that well, I know that "for each write there's a read first" so one has to be sure that or that does not affect what you are doing or have separate addresses for READ/WRITE so they can't be affected.

[edit] - forgot to say, normally, for memories, I do not use /CS at all, /CS I leave it always active and I work of /OE /WE

[edit2] - and still spinning around my mind, it seems to me in 16 bits mode there is no way to distinguish between a BYTE read from an EVEN address and a WORD read, I suppose you can know a byte read at an ODD addres is done via A0 but how could you possibly detect someone is doing a BYTE read when A0 = 0 instead of a WORD read considering that in that case both lines RWHB and RWLB will remain HIGH ?

[edit3] - today I went to have a look in the old attic, I found I still have quite a number of "brand new" still wrapped in foild AMD8521A chips .. could be interesting ?

 

[RSX11M+]

Just a few comments...

• Leaving -CS asserted on memory devices will cause them to draw a lot more power in your system. If you're ok with this, I guess is doesn't matter in this application. However when one has a design with numerous memory devices it's problematic.

• A0 shouldn't be included in "MEMORY READ" on a 16-bit system, because as you say there is no way to differentiate a "word read" of an even address from a "byte read". Besides, a "byte read" from memory is a valid operation regardless of even or odd address.

Once again, 8-bit T-11 modes offer superior cycle differentiation.
​

• In STATIC T-11 modes, ASPI cycles need no differentiation from any other in hardware. I consider it as signifying an "internal CPU" operation. It does not include memory access. AI are inputs at all times in STATIC mode.

In DYNAMIC modes, it's used to differentiate between use of AI lines as OUTPUT during REFRESH vs INPUT during INTERRUPT/HALT/NMI/DMA

If you're not planning to use the CPU to perform DYNAMIC refresh, I see no purpose to recognizing ASPI.
​

 

[RSX11M+]

I think you'll find this thought humorous.

I was letting my mind wander [always dangerous] and thought of a method to differentiate a byte-read from an even address in 16-bit CPU mode. It's a little absurd, hence the humor.

• Your T-11 will operate in 16-bit STATIC mode [no refresh cycles]
• The T-11 is not a "Pipelined" CPU - Therefore SEL<0:1> represents what the CPU is doing on each bus cycle
• SEL = 2 means the CPU is FETCHing an instruction
• A device could therefore watch each CPU instruction FETCH and recognize instructions that would result in "byte-mode" memory access during the EXECUTE cycle(s).

The hardware would require an intimate knowledge of what the CPU is designed to do for each instruction, but it could be made to work.

 

[GilesGoat]

I think you'll find this thought humorous.

I was letting my mind wander [always dangerous] and thought of a method to differentiate a byte-read from an even address in 16-bit CPU mode. It's a little absurd, hence the humor.

• Your T-11 will operate in 16-bit STATIC mode [no refresh cycles]
• The T-11 is not a "Pipelined" CPU - Therefore SEL<0:1> represents what the CPU is doing on each bus cycle
• SEL = 2 means the CPU is FETCHing an instruction
• A device could therefore watch each CPU instruction FETCH and recognize instructions that would result in "byte-mode" memory access during the EXECUTE cycle(s).

The hardware would require an intimate knowledge of what the CPU is designed to do for each instruction, but it could be made to work.

This is "kinda" what the Z80 interface chips do to recognize "RETI" and clear the interrupt condition, the check the /M1 line ( that means the CPU is fetching an opcode ) and the sample the databus as well.

/M1 is low during that cycle so if you'd latch the databus when /M1 is low you precisely get the instruction the CPU is about to execute next ( beware some instructions are multi byte ).

I think in reality is "a non issue" in 16 bits mode, if I understood correctly you can simply return 16 bits always ( during READ ) and the CPU knows what it needs, WRITE is sorted via /WHB /WLB as only one of them is active during BYTE write, both during a WORD write.

Ah true what you say about /CS, by leaving /CS always low you are going to consume more power and you never go into "sleep mode" ( some memories can have it ), however you should also have less power fluctuations.

It really looks like /RAS is designed to be used as a /CS and /CAS for OE/WE ( combined with other signals ) ( well of course they are for the dynamic rams as well ) but I have to say in "more modern designs" I seldom seen RAMs where /CS been not always tied to GND.

Maybe it's one of those "bad modern habits" ?

"Madness for madness" just because you mentioned it I'll have a look to see "how much weird it would be" to implement such a feature, I mean it should be easy to sample the databus and get the instruction then use some kind of "comb" to check all those opcodes that would result in a byte access ( ands, inverters and ors ).

Out of the top of my mind I SUPPOSE one could do something along the lines ( writing just right now out of my head ) :

-- sample on raising edge of CAS IF SEL = 2

process ( CAS )
begin
 if CAS'event and CAS = '1' then
  if ( SEL = "10" ) then instruction <= DAL;
  end if;
 end if;
end process

-- if it's one of those then it's a byte thing

byte_access <= '1' when
 instruction = "00001110110101" or
 instruction = "......................" or
 instruction = "......................" or
 instruction = "......................" or
 instruction = "......................" or
 .. etc. 
else '0';

-- '1' when that byte is accessed otherwise '0'

byte_H = byte_access AND latched_a0;
byte_L = byte_access AND NOT ( latched_a0 );

Something like that .. if I am correct all that "when" thing would translate into an "array" of AND/INVERTERS going into "a big OR"

Could try to see if it's feasible/meaningful to be done

 

[GilesGoat]

So while I was back on the plane I was thinking and reading more stuff.

You say in 16 bits mode I should not be worried about aspi but according to the manual an aspi occurs :

During pup
During halt
During wait

Now, it would seem the only way to distinguish it from an r/w cycle is the fact you have cas with ras at 1 during all time.

There is a catch anyway, during aspi the dal lines are tri stated, this mean I could pull up some of them in order to make out some address range where no I/o stuff is mapped.

The reason is it would allow me to have an I/o decoding where I could consider "good" and I/o address valid and make effective use of ras and cas to generate timings.

Hum.. Or on a second tought maybe is useless because to make an aspi at that address it means it's running an hlt or wait in an address where a device is mapped which would be impossible, about pup one could just watch the pup line.

Maybe I should have slept more on the plane ?

 

[RSX11M+]

While I can understand your wanting to investigate this, I do not think it is cause for concern.

I can see only two possible consequenses... if I look at either one, there is no effect.

1) You are concerned that an ASPI cycle might be interpreted by memory hardware as a valid read. -RAS is high during ASPI so, there should be no read.

However even if there were, I do not see any damage from this. If you wish to prevent it, simply make certain DAL lines default high or low with weak pull-ups or pull-downs so you will be certain the read is performed in an area with no harm. [non-I/O]
​

2) You might be concerned the CPU will be interfered with by data from such a read. The CPU ignores DAL during ASPI, so again this will not be a problem.

As long as you correctly detect the end of the cycle and do not interfere with the next, I foresee no complications.

I have never treated this as anything but one of many possible internal CPU cycles. Other "empty" cycles occur during register operations and when non-memory exchanges are performed. They are common.

Hope that helps... you could have slept, but what fun would that be?

 

[GilesGoat]

I have 4 hours of train today ...

Let's see what else will come out

 

[RSX11M+]

South of France for the day?

How nice.

 

[GilesGoat]

South of France for the day?

How nice.

No, from London Paddington ( after the airport ) to Wales ..

I never been in France in all my life, "so close" and yet never visited that country yet.

I just arrived back here in the country of the sheep, actually this time I spent most of the time back reading OLD Byte magazines and now I am nearly falling asleep.

 

[GilesGoat]

.. and now my brain is melting over PUP and "low to high, high to low" .. etc.

Ok, let's see if I get this correct, PUP is an INPUT that has a pull down resistor and is connected to a Schmitt trigger.

So far, so good.

"As normally seen on various diagrams" one connects a capacitor to VCC and when you power up, initially that will be low, the capacitor charges until it gets to VCC at some point PUP is '1'.

Now 3.5.2.1 page 3-14 .. blah blah .. ok .. and the question is WHAT would make the PUP go LOW again and then start the Mode Register load ?

According to 3.5.2.2 the fact PUP goes HIGH makes BCLR go low.

According to 3.5.2.3 "The Mode Register input begins after -BCRL is asserted ( low ) and PUP is LOW".

Good .. and what makes PUP go low then ? Once that capacitor is charged it should stay as that ..

Also, I think a "Reset" instruction should put -BLCR low but leave PUP untouched, so a certain logic would tell "when PUP is high it should stay high all time".

And then one would think "so it means that the excution of a RESET does NOT re-load the mode register ?".

On the evaluation board schematics they connect PUP via a 2.2 uF capacitor to VCC, all clear EXCEPT that "how PUP goes HIGH TO LOW to start that sequence then ?".

This PUP story is not very clear ...

The powerup sequence at page 3-15 clearly shows PUP going LOW to HIGH to LOW .. but what makes that last HIGH-TO-LOW thing is puzzling me.

Strange is it ?

[edit] - all this for a couple of reasons but what "makes me crazy" is that diagram at page 5-2 figure 5-2 where you clearly see they want -BLCR low AND -PUP LOW to say "ok now you can give stuff for the Mode Register".

In all other diagrams I've seen so far they blatantely ignore PUP, they just would connect -BCLR and nothing else to that '244 ( or as they do in the evaluation module they use it to drive a set of open collector inverters ).

I am asking myselg "who is more right and what consequences there could be in doing one way or another ?"

 

[GilesGoat]

South of France for the day?

How nice.

.. in 200x I can't remember at the last min when they were announcing the gate I managed to mis-listen "Nice" for "Venice" and I went to the wrong gate.

You would not believe but at the gate they boarded me up and I was already sit on the plane when the doors were almost getting closed when I heard a never heard before annoucement in French.

I managed to board the WRONG plane going to Nice instead that Venice.

Funny thing I suspect "it never happened before" and I had quite a bit of nightmare to re-cover ( or better get a new one ) the boarding pass and board the right plane, the boarding pass was already processed into the system and "for everyone" I was going to Nice.

I remember quite some people "getting nuts" asking me "how did I do it ?" and I told them "well, I simply went to the wrong gate when they called it", note that they did ask for my passport and all and the card been processed by the machine so "fantastic software" I suppose ...

I won't tell you what airport it was ( one in UK ).

 

[RSX11M+]

.. and now my brain is melting over PUP and "low to high, high to low" .. etc.

Ok, let's see if I get this correct, PUP is an INPUT that has a pull down resistor and is connected to a Schmitt trigger.

So far, so good.

"As normally seen on various diagrams" one connects a capacitor to VCC and when you power up, initially that will be low, the capacitor charges until it gets to VCC at some point PUP is '1'.

I think the misunderstanding is here already.

• The idea here is that at power on, there is no charge in the capacitor. Instantaneously, when power is applied, PUP goes to 1. [VCC]

• -BCLR will be asserted [LOW] shortly after.

• The Capacitor then slowly [by comparison] "charges" through the internal pull-down in the CPU. During this "Charge accumulation" PUP is dropping in voltage with respect to VSS.

• When it reaches the voltage for a valid low, the internal reset within the CPU will go away. This begins the actual CPU initialization sequence described on page A-52.

• -BCLR is still asserted [LOW] at this time. The CPU performs it's internal initializations and then samples the MODE setting bits on successive bus cycles. [with -RAS, -CAS and other control signals negated, except COUT]

• When the final MODE bit has been sampled, -BCLR is negated [HIGH].

Now "normal execution" begins and the first bus transactions occur per the MODE settings intended by the designer. [You?]

PUP is now static for as long as power remains stable.

Application Note:

** This kind of power-up sensing is not really very good because it requires a fast "turn on" edge to primary power, and that it be stable thereafter. It would never do for an unattended or high reliability system.

Slow variations in supply voltage will succeed in causing CPU or memory errors and possible failure to start.

This is a common design problem in many microprocessor systems and operation will be far more stable through power interruptions if a specific chip like the MAX706 is used to condition PUP. This is especially important where CORE or RAM is expected to be non-volatile via battery backup. I will provide a detailed treatise on this if you like.
​

From this point out, I think you were on track.

I'm really very impressed by your depth of understanding of this material. Your questions are insightful, observations relevant, and I believe you will very likely turn out a working project on your first attempt.

 

[RSX11M+]

.. in 200x I can't remember at the last min when they were announcing the gate I managed to mis-listen "Nice" for "Venice" and I went to the wrong gate.

You would not believe but at the gate they boarded me up and I was already sit on the plane when the doors were almost getting closed when I heard a never heard before annoucement in French.

I managed to board the WRONG plane going to Nice instead that Venice.

Funny thing I suspect "it never happened before" and I had quite a bit of nightmare to re-cover ( or better get a new one ) the boarding pass and board the right plane, the boarding pass was already processed into the system and "for everyone" I was going to Nice.

I remember quite some people "getting nuts" asking me "how did I do it ?" and I told them "well, I simply went to the wrong gate when they called it", note that they did ask for my passport and all and the card been processed by the machine so "fantastic software" I suppose ...

I won't tell you what airport it was ( one in UK ).

LOL - certainly not the funniest travel mistake I can tell of. It must have made them crazy. That kind of thing isn't supposed to be possible these days.

I can tell you this story because it happened years ago, and the statute of limitations has run out on it.

I was working in Los Angeles on a business trip that was several weeks long. Instead of flying, I decided to drive. No big deal, I like to drive, my car was new - and it saved me having to put up with the expense an inferior rental car.

Anyway, one morning at about 3:00am I get a phone call. Once I come out of my stupor, I find myself stalking to my friend, here at home in Ohio. He's calling me to ask a favor, and that I meet his Girlfriend, who has also traveled to Los Angeles for the Christmas holidays. He tries to explain to me that she's accidentally taken her loaded pistol with her on the plane among her Christmas gifts.

Apparently she realized her mistake well after takeoff. She sailed through security without any problem whatsoever.

I begin laughing hysterically. It amuses me to this day. For years I couldn't tell anyone it happened for fear of causing her problems.

Anyway, I met her and took the pistol back home with me by car, without further incident [on that trip].

 

[GilesGoat]

I'd be interested to see that circuit because after quite some thinking/studying I see it's not so trivial.

PUP has to go from 0 to 1, stay 1 at least 100 us and then go 0 again.

The thing I could see is that you could use TWO of those MAX chips, one with a time constant T1 and one T2 > 2 and feed that to a XOR gate ( or sorta ) and you have to choose such T2-T1 >= 100 us

Those chips are not really cheap.

I was thinking if maybe I could "replace" those with a NE556 or such, the XOR gate could be made into the CPLD, I think anyway you need a MAX707 that has an active high reset out.

If I understand correctly the MAX7xx guarantees you that as long as VCC is below a thresold /RESET is low, when VCC is at correct voltage RESET will stary low for 200 ms more then it will go high ( and stay high ).

It's a bit tricky because what you want is a "pulse" not just "an edge" ..

Unless in some way you could use the fact that PUP is pulled low already, at power up before the MAX reaches the threshold PUP is already low for a little then the MAX begins to stay high and then finally it goes low again.

Not sure really if this would work and how ..

[edit] .. still spinning into my mind ( and now I better work on something else ) ..

Did not quite understand well how that chip works, but I suppose you could use the MAX813 and connect the /WDO to /MR and someway use the WDI input as well ( connected to VCC maybe ?) this should generate a pulse on RESET ?

 

[RSX11M+]

Umm... I guess I've confused the issue by introducing the MAX706. Sorry.

• I think your system will be fine with the Capacitor.
• Did you follow my explanation of the Capacitor based reset? It does exactly what you say [which is correct] Makes PUP high when the system is powered up, then after ~1 time constant, PUP goes low. 2.0uf will provide a nice long reset.
• A Pushbutton switch [N.O.] across the capacitor will allow you to have a manual reset.

My systems are [were] usually intended to be run with no human presence. So they had to power up cleanly, and if they ran "off track" - correct themselves. The 706 is a "Watch-dog" and a Power Monitor. This chip was part of those precautions. It's probably overkill for your needs here.

However, to discuss your final point - the MAX706 "-RESET" output is inverted from your precise needs. Connect it to PUP via an inverter. As I think you were pointing out, the 707 or 708 provide both RESET and -RESET, and eliminate the "Watch Dog" function.

I hope I've helped with this post.

 

[GilesGoat]

Umm... I guess I've confused the issue by introducing the MAX706. Sorry.

• I think your system will be fine with the Capacitor.
• Did you follow my explanation of the Capacitor based reset? It does exactly what you say [which is correct] Makes PUP high when the system is powered up, then after ~1 time constant, PUP goes low. 2.0uf will provide a nice long reset.
• A Pushbutton switch [N.O.] across the capacitor will allow you to have a manual reset.

My systems are [were] usually intended to be run with no human presence. So they had to power up cleanly, and if they ran "off track" - correct themselves. The 706 is a "Watch-dog" and a Power Monitor. This chip was part of those precautions. It's probably overkill for your needs here.

However, to discuss your final point - the MAX706 "-RESET" output is inverted from your precise needs. Connect it to PUP via an inverter. As I think you were pointing out, the 707 or 708 provide both RESET and -RESET, and eliminate the "Watch Dog" function.

I hope I've helped with this post.

I think I was confusing this :

VCC --[resistor] -- + --- PUP
                           !
                           !
                          Cap
                           !
                           !
                          GND

With this

VCC --Cap -- + --- PUP
                    !
                    !
                [Resistor]
                    !
                    !
                  GND

In the first case, it would do exactly the opposite, the second case it's what happens in the T-11.

However I will have a bit of more thinking around this.