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Project to create an ATX 80286 mainboard based on the IBM 5170

I have looked at the contents of the JED files found in the mame download as Sergey pointed out.
I wanted to see if I can create some equations which can be used in a schematic representation of the PAL16L8 chips on the 5170 mainboard.

However something is not as I expected in these files.

U87 in the IBM 5170 schematics is a key component for buffer control and DMA control.
In the IBM schematic it is shown as having 13 inputs and 5 outputs.
So we would expect to see something along those lines as inputs and outputs.

When looking at the U87 JED file which should represent a PAL16L8, I am seeing this:

JEDEC file generated by BP-1200/48/SM48D from PAL14L4 02/13/11 21:27:38*
DM MMI(AMD)*
DD PAL14L4*
QF448*
G0*
F0*
L00000 0000000000000000000000000000*
L00028 0000000000000000000000000000*
L00056 0000000000000000000000000000*
L00084 0000000000000000000000000000*
L00112 0000000000000000101010100000*
L00140 0000000000000000101010100000*
L00168 0000000000000000000000000000*
L00196 0000000000000000000000000000*
L00224 0000000000000000000010100000*
L00252 0000000000000000000010100000*
L00280 0000000000000000000010100000*
L00308 0000000000000000000010100000*
L00336 0000000000000000101010100000*
L00364 0000000000000000101010100000*
L00392 0000000000000000101010100000*
L00420 0000000000000000101010100000*
C02A8*
8B9A


The JED file contains a reference to a PAL14L4 part, which can't match with the IBM schematic as you would expect..
Since the schematic has 5 outputs that we need the logic equations for.

I tried the OPALJR JED2EQN which results in this:

; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063)
; Copyright (c) National Semiconductor Corporation 1990-1993
; Disassembled from U87.JED. Date: 7-28-123

chip U87 PAL14L4

i1=1 i2=2 i3=3 i4=4 i5=5 i6=6 i7=7 i8=8 i9=9 GND=10 i11=11 i12=12
i13=13 o14=14 o15=15 o16=16 i18=18 i19=19 VCC=20

equations

/o16 = i2 * /i2 * i1 * /i1 * i3 * /i3 * i19 * /i19 * i4 * /i4 * i18 * /i18
* i5 * /i5 * i6 * /i6 * /i7 * /i13 * /i8 * /i12 * i9 * /i9 * i11
* /i11
+ i2 * /i2 * i1 * /i1 * i3 * /i3 * i19 * /i19 * i4 * /i4 * i18 * /i18
* i5 * /i5 * i6 * /i6 * /i7 * /i13 * /i8 * /i12 * i9 * /i9 * i11
* /i11
/o15 = i2 * /i2 * i1 * /i1 * i3 * /i3 * i19 * /i19 * i4 * /i4 * i18 * /i18
* i5 * /i5 * i6 * /i6 * i7 * /i7 * i13 * /i13 * /i8 * /i12 * i9
* /i9 * i11 * /i11
+ i2 * /i2 * i1 * /i1 * i3 * /i3 * i19 * /i19 * i4 * /i4 * i18 * /i18
* i5 * /i5 * i6 * /i6 * i7 * /i7 * i13 * /i13 * /i8 * /i12 * i9
* /i9 * i11 * /i11
+ i2 * /i2 * i1 * /i1 * i3 * /i3 * i19 * /i19 * i4 * /i4 * i18 * /i18
* i5 * /i5 * i6 * /i6 * i7 * /i7 * i13 * /i13 * /i8 * /i12 * i9
* /i9 * i11 * /i11
+ i2 * /i2 * i1 * /i1 * i3 * /i3 * i19 * /i19 * i4 * /i4 * i18 * /i18
* i5 * /i5 * i6 * /i6 * i7 * /i7 * i13 * /i13 * /i8 * /i12 * i9
* /i9 * i11 * /i11
/o14 = i2 * /i2 * i1 * /i1 * i3 * /i3 * i19 * /i19 * i4 * /i4 * i18 * /i18
* i5 * /i5 * i6 * /i6 * /i7 * /i13 * /i8 * /i12 * i9 * /i9 * i11
* /i11
+ i2 * /i2 * i1 * /i1 * i3 * /i3 * i19 * /i19 * i4 * /i4 * i18 * /i18
* i5 * /i5 * i6 * /i6 * /i7 * /i13 * /i8 * /i12 * i9 * /i9 * i11
* /i11
+ i2 * /i2 * i1 * /i1 * i3 * /i3 * i19 * /i19 * i4 * /i4 * i18 * /i18
* i5 * /i5 * i6 * /i6 * /i7 * /i13 * /i8 * /i12 * i9 * /i9 * i11
* /i11
+ i2 * /i2 * i1 * /i1 * i3 * /i3 * i19 * /i19 * i4 * /i4 * i18 * /i18
* i5 * /i5 * i6 * /i6 * /i7 * /i13 * /i8 * /i12 * i9 * /i9 * i11
* /i11


Where I am seeing only 3 outputs instead of 5 outputs.

There is another matter which can't be right, in the U130 JED file, also a PAL16L8 part,
I am seeing this:

JEDEC file generated by BP-1200/48/SM48D from PAL14L4 02/13/11 23:50:18*
DM MMI(AMD)*
DD PAL14L4*
QF448*
G0*
F0*
L00000 0000000000000000000000000000*
L00028 0000000000000000000000000000*
L00056 0000000000000000000000000000*
L00084 0000000000000000000000000000*
L00112 1111111111111111111111111111*
L00140 1111111111111111111111111111*
L00168 1111111111111111111111111111*
L00196 1111111111111111111111111111*
L00224 1111111111111111111111111111*
L00252 1111111111111111111111111111*
L00280 1111111111111111111111111111*
L00308 1111111111111111111111111111*
L00336 1111111111111111111111111111*
L00364 1111111111111111111111111111*
L00392 1111111111111111111111111111*
L00420 1111111111111111111111111111*
C29D6*
8CD0


This doesn't look right either.
From the resulting EQN file it's apparent that this also cannot be correct to represent the part on the 5170 mainboard:

; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063)
; Copyright (c) National Semiconductor Corporation 1990-1993
; Disassembled from U130.JED. Date: 7-28-123

chip U130 PAL14L4

GND=10 o14=14 o15=15 o16=16 VCC=20

equations

/o16 = vcc
+ vcc
+ vcc
+ vcc
/o15 = vcc
+ vcc
+ vcc
+ vcc
/o14 = vcc
+ vcc
+ vcc
+ vcc


I don't know why these JED files are specified in this manner, but I can't rule out that this is perhaps specific for emulation purposes only.

I will spend some more time searching for other information about the 2 PAL16L8 contents equations, maybe I can find them somewhere.

Additionally, I have indeed seen this information confirmed in some PAL16L8 datasheets, there is a mention of a retention time of ">20 years".
This doesn't indicate exactly how long the theoretical retention is, but it does make me ask myself if perhaps these old PAL chips are going to fail eventually.
Perhaps that's exactly what happened with my ARC mainboard which suddenly stopped functioning reliably after a sudden power drop when I accidentally shorted VCC to GND on a pinheader.
The power supply when into protection mode, but after I turned it off and back on, there was a big stability problem in hardware detection on the ISA bus.

Kind regards,

Rodney
 
Hello Rodney

I think your project is very interesting. Specially I am interested in a design which uses as much discrete logic as possible. Perhaps only a few PALs or GALs, and even without them, if that is possible. Which does not mean that afterwards it can be done a replica using only FPGA. But discrete logic, seems to me that it could be more easy to understand

I was interested in doing something similar, although I must recognize for me is not a realistic goal, as I my knowledge on the hardware side is very limited. My experience is from the software side of things, and more on other architectures than with the x86 architecture.
So in the short/medium term, I am interested in following other persons designs on this regard, although I could try to help in some way with this goal (perhaps software or in other way).

I saw a YouTube video in which it was replaced the 286 processor on a main board, with a 386SX replacement that can be plugged in the 286 socket, that had only a 386SX processor with just a pair of discrete logic chips (probably 74x00 series), so I thing it is posible to make a 286 board, and with very few modifications, make it work with an 386SX , which would give you access to 32 bit software without the limitations of a 286

In case you are not aware, please take into account that power connectors for 386 boards are different from modern ATX connectors, although there are adapters that make possible to power them with modern ATX power supplies.

I bought two months ago an old 286 board with discrete logic. As you have said, it was sold untested. And it is a shame, but I have still not tested it. Due to some personal problems I have been unable to have spare time for this things.
Perhaps from now on I could take some spare time for this things, from time to time.
We could talk about the possibility to lend it to you for a period of time. We can talk it through our personal e-mails, if you agree with that.
I have a 286 computer on my parents basement (as I have little space on my flat), and I think it uses discrete logic on its main board. But I think it is too precious for me to lend it, although we can talk on that.
I bought the old 286 mainboard, specially in order not to damage my own 286 computer.

There are a few web links and YouTube videos related to, I think two french students who investigated the first AT designs, and a design of a Intel 80386SX development board. Seems are in some way related to an LSE french institution.
Unfortunately, the videos are in french language, although you can configure YouTube to translate it to English, but it does not translate it well.
("Early PC architecture - Rémi Audebert - LSE Week 2015")
("Introducing the LSE-PC - Pierre Surply - LSE Week 2015) (seems to be based on the previous video)

And I attach here a web link to the 80386SX development board they designed.
https://blog.lse.epita.fr/2015/11/16/lsepc-intro.html ("Designing an Intel 80386SX development board")

At retrobrewcomputers.org there is a design for a 386EX board.

Also, here is a design for a 386DX single board computer. It has schematics and pcb design, BUT it is based on a chipset. On this web site, there are also designs for graphic card, debug card, etceterea

Here is a PCB specification for a 386SX board, also for a specific chipset, but perhaps it is useful for you for reverse-engineering. there is also one or two YouTube videos on it, if I recall it right. BUT it is based on a chipset. And lacks schematics, it would require reverse-engineering:

In case it is useful, I attach here the link for a "work in progress" design for a 486. It is a bit different approach from yours:

Sorry for my too long post, I tried to include the information I have

Regards,
Alvaro Garcia
 
Hello Alex, Rodney

Thanks Alex for your greetings

Rodney and everybody:
Regarding the EPITA/ELS french project, there is also other possibly useful links.
This one is a document on "Early PC Architecture":

Github repo of the board they designed. Well, this design is based on an FPGA .... but perhaps there is useful information there. On my previous post I included a web page with the design. Here es the details of the specification:

Regards,
Alvaro Garcia
 
IMHO, one of the bigger hurdles with implementing an IBM PC/XT/AT clone is to properly emulate/implement on-board peripherals and ISA bus behavior.
The designs listed above avoid this issue in different ways:

There are a few web links and YouTube videos related to, I think two french students who investigated the first AT designs, and a design of a Intel 80386SX development board. Seems are in some way related to an LSE french institution.
Pierre's LSE-PC does not in fact implement PC/AT compatibility. It implements a simple system with 386SX, that provides memory (SRAM) interface, and debug interface, that allows experimenting with 386SX.
There is no DMA, timers, interrupt controllers, keyboard controller, ISA bus. I doubt it can run any DOS software at all.

Also, here is a design for a 386DX single board computer. It has schematics and pcb design, BUT it is based on a chipset. On this web site, there are also designs for graphic card, debug card, etceterea

Here is a PCB specification for a 386SX board, also for a specific chipset, but perhaps it is useful for you for reverse-engineering. there is also one or two YouTube videos on it, if I recall it right. BUT it is based on a chipset. And lacks schematics, it would require reverse-engineering:
Both of these designs, are chipset based. So chipset implements all the the IBM AT compatibility and ISA bus. The major drawback is that chipsets are becoming scarce (they weren't manufactured since mid 90's or so).
There are some other drawbacks. For example, some chipsets only come in flatpack packages, which are not hobbyist friendly. Another drawback is that chipsets were typically designed to work with DRAMs, and so building a system would require sourcing these DRAMs/SIMMS... Currently, for systems with not a lot of memory, using SRAM might be a better approach, or, if more memory is desired, it might be preferable to use a more modern DRAM technology, e.g. DDR.

In case it is useful, I attach here the link for a "work in progress" design for a 486. It is a bit different approach from yours:
This to be a "breakout" board for 486. It is far from having PC/AT compatibility. Good for experimenting, not good for running PC software
 
Both of these designs, are chipset based. So chipset implements all the the IBM AT compatibility and ISA bus. The major drawback is that chipsets are becoming scarce (they weren't manufactured since mid 90's or so).
There are some other drawbacks. For example, some chipsets only come in flatpack packages, which are not hobbyist friendly. Another drawback is that chipsets were typically designed to work with DRAMs, and so building a system would require sourcing these DRAMs/SIMMS... Currently, for systems with not a lot of memory, using SRAM might be a better approach, or, if more memory is desired, it might be preferable to use a more modern DRAM technology, e.g. DDR.
My idea regarding the two cases with chipsets designs is that ithat chipset is more or less documented, perhaps "emulating" that chipset, the advantage is that at least all the other things arround it are already impplemented, and perhaps it could be a way to divide the effort by two.
But I recognise that the chpset is perhaps the core of what has to be designed, so the possible aid is probably little, if any.

@Sergei, one question (really two)
8088 designs could be a good base to design an AT clone, or are they completely different, and you have to start from zero?
Or perhaps the "breakout" board for 486 could be a good base for achiving PC/AT compatibility?

Regrads,
Alvaro Garcia
 
Hi Alvaro,

Thank you for joining this forum and replying on my thread with many interesting details, I appreciate your time and effort!
Thanks for offering your help, I will post further details as soon as I get started on the project, and if you feel you can help in some way, please feel free to let me know. Definately I have very little programming experience, so who knows, maybe you could be of help later on.

I think that this project involves so many details that it's easy to end up with longer messages, for the interested readers I am sure they can enjoy the discussions here.

After reading your messages, I think that your motivations of wanting to do such a project are the same as mine. I also want to recreate a classic system that was very important because it's at the start of the AT PC standard. These days when someone talked to me about buying an "AT PC" back in the day, I do get excited thinking about the history and my project. And at the same time I'm thinking, I wish they still own it and I can study it in detail. But of course, most of them are discarded and gone.

I'm the same, I first want to capture the technology and then I don't really care if I need some PAL chips or others. I also prefer normal glue logic in the first concept circuits to keep a good perspective on the entire design, though it may pose some problems if they prove not fast enough, we will see...

The SX type CPUs I think they are all compatible with the 286, so it should not pose a big problem to use the 386 or 486 type 16 bit CPUs. At higher clock speeds there will be a certain point when we will be needing FPGA or at least a fast CPLD to reach a working timing speed. Using a programmable chip in a later stage at least allows for some timing adjustments if needed.

My first prototype will be very similar to the first IBM AT design, which I really love so it's well worth replicating that first.
After that project is finished I will definately look at the 486SLC. I think I will skip the 386 because I feel it's not really worth the extra effort historically. So just move on to the fastest alternative. I would also consider an emulated CPU at this stage just to explore what the limits are of such a system.

About power supplies, I will simply keep the full size ATX form factor and power supply connector. It's already featured on my XT design which you can see on Github.

I had a lot of bad experience so far with discrete AT mainboards. Right now I believe the most sensitive parts on these mainboards will be the PAL and PROM chips. Also those 4 layer PCBs may be prone to develop broken traces if they are not handled properly in their lifetime. I think later PCB technology developed a higher reliability level on multilayer boards.

In my life there are also some "difficulties" which has stopped my development somewhat recently because my attention is suddenly needed on other urgent stuff happening. Hopefully you can solve the problems, I'm also working on the stuff going on here so I can have more time for other things again. These projects are really healthy for the mind and the more you do them, the design level also will improve over time, which is what I'm enjoying too when I look at the results of my XT project. I'm looking forward to similar experiences with the AT system.

Thanks for your offer to lend me your untested AT mainboard. I already invested in buying two mainboards, and I will also be buying a Hakko desoldering iron, because I get tired of the bad quality Chinese ones. I am considering to buy a 5170 for reverse engineering the PALs and PROMs and other testing work but at the moment I am not having a lot of space where I am at the moment, after I move it will be better in the future. Anyway, a 5170 is a big investment with the current prices, so I will wait until the right moment to do it. Thank you, I would like to talk with you about the possibility of lending your mainboard to me, let's exchange some mails to talk about that. Definately I can understand you don't want to open up the original 286 which has some sentimental value for you. These systems are sensitive and that's another reason why I feel it's important to document all the technology very carefully in a full working design replica. That way, if one of the original systems dies, there is a bigger chance to recover and repair all of them. The first and most important step is to obtain a working reference model and build a full working design on that. I feel this is also of a historical importance, when I look at my two 286 mainboards which both have issues.

I will study the French project in more detail, if it could be of some use I could contact them. My first step that I want to take is to exactly document how IBM did their 5170 programmable logic parts. In other clones, I am sure it's basically following their concept mostly when you look at the other logic on those boards.

I just wanted to reply you first these things, I will continue tomorrow when I can find more time. I am also very interested in those other projects you mentioned!

Kind regards,

Rodney
 
Hello Rodney

I will try to answer some things and add some more information.

[Rodney] > I think that your motivations of wanting to do such a project are the same as mine.
Yes, I also think my motivations are very similar.

@rodney I attach here my e-mail: ramon_blake@yahoo.es
Please write me over there or leave on this blog your e-mail, and we can talk on the possibility of lending the board, and perhaps other things

Regarding the french project, I think you are right, they achieved a wealth of information, and their project (really two projects) seem very similar to yours (and also my humble aim or purpose).
So if they are still reachable by e-mail, IMHO they can give you much information.
I see to french projects:

* one investigating early PC architecture (mostly PC/AT). I think this one was done mostly by Remi Audebert
Of this you have, at least (mentioned on previous post):
- video "Early PC architecture - Rémi Audebert - LSE Week 2015"
- PDF document: lse-summer-week-2015-12-pc_Early_PC_Arquitecture.pdf

* one recreating an Intel 80386SX development board with an 80386SX + an FPGA. It seems it has been done at least mostly by Pierre Surply
Of this you have (mentioned on previous post):
- video "Introducing the LSE-PC - Pierre Surply - LSE Week 2015"
- documentation on link: https://blog.lse.epita.fr/2015/11/16/lsepc-intro.html
- Github repo: https://github.com/psurply/lse-pc

I can send you the e-mails of both of them to your own e-mail, if you want.
It seems to me that Remi Audebert and Pierre Surply probably worked on each others work. Remi Audebert based his investigation on PC/AT documentation, and also on a 386SX board.

I am thinking that for debugging purposes, it could be useful to make a breakout board, or a board with leds, plugged to the 16-bit ISA bus, so that it gives you information on all the signals on the ISA bus.
Rémi Audebert created one (you can see it on his document) whose image I attach below.
Alexandru Groza (mentioned on previous post) created also a board for debugging. I attach image below.
Fox Cutter is creating a support board for his 486 project, which references 486 signals. Nowadays it also includes the porwer suply logic, although I think he is planning to move the power suply logic to the backplane. I attach (blurred) image below from his YouTube video. He has a github repo, I don`t know if it includes it last designs of this project:

I am thinking that perhaps I could do this breakout (or led) board some day, who knows! 8-)

Alexandru Groza (and others) has also a design for a ISA backplane.

@rodney. One question: I understand that your design will be for a 386 or 486 SX (or SL?) variant. Correct?

Another thing. I would like to humbly suggest that your design has at least 8 Mb of RAM. This is because Linux kernel needs at least 8 Mb in order to boot. Arguably, it could boot on a 4 Mb of RAM. And that is only true for the very oldest versions of Linux. I remember that the first versions of Linux that I installed were on a 32 Mb computer.
One alternative could perhaps be to try to install the XV6 operating system on it, which would require less memory, perhaps it can run on 512 kb (or less?)

One last note. I have some limitations on what time I can dedicate to this PC/AT project. But I am interested on it, so the future will say how much I can do to help, both in effort and time, and also on knowledge.
As I have said, on the hardware side I am learning as much as I can on these last months, as my background is mostly on the software side, and all of it is self-taught and what I learned at my job.

I hope the information on this post is useful

Regards,
Alvaro Garcia
 

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Hi Alvaro and Sergey,

Thanks for your replies and effort to find and looking at these other projects. Though the level of result is uncertain for the French projects, perhaps I can talk with them later on for my follow up projects, since at a certain point it may become a larger work, I wouldn't mind, if the project needs it, to collaborate with some people skilled in FPGA coding with a similar interest in IBM PC architecture. For that purpose, I may like to get in touch with the French project users later on to see if they have some interest in this.

For my current project of this thread I already have an instinct about in what direction I will need to proceed in order to have the best chance of success and getting a system to be solid and sound. The plan is not my problem, my problem is to make enough time, which I am solving, and the other problem is needing a reference mainboard which is 100% reliable and stable. With the AT design this is even more crucial than in the case of my XT project, because as we discussed before, the 5170 PAL codes are not documented in a workable format anywhere, at least I have not seen one yet. No PAL code means no complete usable circuit diagram, that is the reality from my perspective.

The 5170 is in areas similar to the XT, so I will approach the project in the same manner as my XT project, which is:

- very important first step: I need to use a working reference mainboard similar to the 5170. Whether this will be an IBM or some clone, is not that important. Stability is. First thing I will do is do a complete test to check that there are no defects or errors.
- next step: (desoldering if needed and) reading out the PAL ICs as a ROM image
- decode the ROM code results using special software
- comparing the PAL equations to the whole circuit to see if they make sense
- composing a circuit diagram in structural areas and sections based on the IBM schematic and PAL code equivalent circuits
- I will do the memory design as Sergey also mentioned, I totally agree with Sergey, using SRAM is best for this type of system. This method will remove the DRAM and parity checking logic areas from the system which are quite a number of ICs already. Using larger capacity and more modern RAM components (4 megabit) will also simplify the memory decoding and reduce drive current for the memory.
- where possible, I will drive the bus using HCT logic which results in much better amplitude shapes
- I will use an ATX power supply and as I mentioned also a proper reset drive timing, which does need improvement from the IBM circuits
- First I will design and build one or more revisions of the 286 AT mainboard similar to a 5170 until it's a fully developed and satisfied concept to me in similar spirit as my XT, and then I will proceed to the 486SLC version based on that. I can't skip the 286 stage because I first need a good concept of the 16 bit AT design suitable for upgrading the design to 486SLC later in the 486 project I will be doing at some point.

So far I have (thankfully! ;) ) not needed a breakout PCB yet, because I take a long time to prepare and examine the circuits first. However it does seem handy to have one. Especially to have some useful and accessible pin connectors for securely attaching scope probes would be useful indeed, and the corresponding ground connection terminals for example for an alligator clip. And a lot of ground plane for solid measurements. And perhaps adding a POST code display, and even a second ISA slot on top for plugging in a card which you can then easily probe when it's sticking out of the PC case. I have seen this method being used on some very old mini computer systems(which I love!) where he probed and checked a drive interface card outside the case. Alexandru's card is the most cool one! However many signals may not be possible to monitor them by vision. It just looks cool though!

I will get in touch with you by email to your address soon, so we can talk about possibly using the mainboard you bought as a reference for the project. I can inform you of my progress and provide some of my schematic stages and notes as a thanks. I will publish the AT mainboard on Github as well, so anyone interested and capable to make it can order a PCB and make their own.

I will look at the French projects in more detail. As Sergey also mentioned, chipset variants are not that interesting for this project because everything is hidden design inside the chipset ICs. Knowing the contents of a chipset would be a huge help though, but since open source is something of late and not of the 1980s, I doubt this will ever happen.

As for the M396F, I also own an original old one, I bought it from an Italian ebayer with some adapter cards, it was so badly "etched" by battery liquid I thought it was lost but I managed to save it anyway, photo below. I love this compact design integration though. Sorry to strip out those ISA slot connectors because I needed them for my prototypes. Later when I buy a new Hakko I will put them back from my old revision prototype PCB which I don't need anymore. I am still searching for the right MR BIOS for this M396F board, it's not anywhere online. This type of closed "chipset" mainboard is to me not an interesting project. Some people may object me saying this, but I feel that using a chipset is more easy in design level than the 5170 and possible derivatives. This is part of why I like the 5170 so much, because that one is still some really pure original IBM design work before everything got so messy in PC evolution and competition, and deeply buried inside chipset ICs.

Some people even call certain circuits in the 5170 "IBM's secret sauce", I love this remark, especially while looking at these circuits!

So I am going to work hard to keep the full "secret sauce" complete and alive and not let the historical design become extinct! I really believe that PALs are possibly prone to break down after many years so documenting them is very important in my opinion to be done.

Kind regards,

Rodney
 

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Hello everyone,

Rodney, Sergey, I agree with you, for me also the goal would be to reverse-engineer the 5170 IBM PC and, at least the first prototypes, to make them with discrete logic (no chipsets) and as the most, some PALs.
At least for beginners in digital electronics (like me), I think that is more clear and less abstract that FPGAs or CPLDs.
I think that afterwards it could be easier to understand the conversion to a an FPGA prototype, if that is ever done.

I attach images of the 286 to 386SX upgrade I saw on the YouTube video with the title:
"286 Boost! Upgrade to 386 or additional Cache ~~ODD PARTS~~" of the channel "CPU Galaxy"

That upgrade can be inserted on the 286 PLCC socket, and substitute de 286 CPU with a 386SX CPU
The pity is that the conversion is not so straightforward, because in addition to the two 74373 bus drivers, it uses an intel PLD chip.

Regarding the "chipset projects" (and FPGA project) I only included them in case they are useful to reverse-engineer things, although it is clear that inside the chipset is "black box".
For at least one of this two chipsets mentioned, I founded documentation, but it only includes information on the signals of the pins, the functionality that it provides, etcetera.

Regards,
Alvaro Garcia
 

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FWIW, I do own a discrete-logic (no chipset) 20MHz 80386 system. The main planar is so crammed with logic (full-sized PC AT profiel) that the RAM is on a separate board. Nowadays, RAM shouldn't be a problem--8MB PSRAM chips are quite plentiful.
 
Hello everyone,

Rodney, Sergey, I agree with you, for me also the goal would be to reverse-engineer the 5170 IBM PC and, at least the first prototypes, to make them with discrete logic (no chipsets) and as the most, some PALs.
At least for beginners in digital electronics (like me), I think that is more clear and less abstract that FPGAs or CPLDs.
I think that afterwards it could be easier to understand the conversion to a an FPGA prototype, if that is ever done.

I attach images of the 286 to 386SX upgrade I saw on the YouTube video with the title:
"286 Boost! Upgrade to 386 or additional Cache ~~ODD PARTS~~" of the channel "CPU Galaxy"

That upgrade can be inserted on the 286 PLCC socket, and substitute de 286 CPU with a 386SX CPU
The pity is that the conversion is not so straightforward, because in addition to the two 74373 bus drivers, it uses an intel PLD chip.

Regarding the "chipset projects" (and FPGA project) I only included them in case they are useful to reverse-engineer things, although it is clear that inside the chipset is "black box".
For at least one of this two chipsets mentioned, I founded documentation, but it only includes information on the signals of the pins, the functionality that it provides, etcetera.

Regards,
Alvaro Garcia

There is a bit here on the PLD interfacing the 386sx to the 286 chipset with schematic and code

and an implementation of that on a 286 project board here
 
There is a bit here on the PLD interfacing the 386sx to the 286 chipset with schematic and code

and an implementation of that on a 286 project board here
Hello Theoryboy, your videos look awesome!
Thanks for the post.
I think that the the possibility to, based on the 286 design, jump into a full 32 bit cpu is very exciting!

Regards, Alvaro Garcia
 
Hello Theoryboy, your videos look awesome!
Thanks for the post.
I think that the the possibility to, based on the 286 design, jump into a full 32 bit cpu is very exciting!

Regards, Alvaro Garcia
Hi, would like to clarify they are not my videos, they are from @rehsd_info , but they are informative for sure
 
Hi Theoryboy,

Thanks for your post. I have checked the PDF and also some of his videos. I saved the PDF, it could prove to be useful when I research a future 486SLC upgrade project.

I tried to get into his projects but from the videos and blog at first glance it's a little hard to understand what he is doing, I guess I need more time to watch and read but there are so many videos, I simply can't watch all of them to get the complete picture. There doesn't seem to be any single page which outlines in what way he is trying to build a 286 PC. I mean, there is an index with green tick marks of his progress but I am not seeing any clear information which explains his method. I think a clear outline and simple explanation of the system as a whole would make the project more accessible for more visitors. It will be interesting to some day see his end result though because it might inspire new ideas for future projects.

Kind regards,

Rodney
 
Hello everyone,

I want to update on my project to those who are interested and following this thread.
Right now my situation is not ideal so I am adjusting the work to the essentials until I can clear up the stuff which is going on.
I am still on the hunt for good specimens which can serve as the definitive reference board for my project.

From this reference board, once I have found it, restored it in optimal condition and determined it's stable, durable and fully working, I will proceed to first obtain the PAL and PROM logic.

Then I will compare with the IBM schematics to determine the pin names and functions of the PALs used, to try to see if the PAL equations can make sense in the context of the IBM 5170 schematics.
If that is the case, or in a slightly modified/updated state of the IBM circuits which will also suffice, I will proceed to draft the core schematics which compose the base mainboard functions.
Next step will be to add all the base interfaces such as floppy, IDE, serial, parallel, LAN, SCSI, etc.

I have recently found a second ARC X286 Model 12 mainboard. It's missing the CPU and the socket and slot bracket plastics are slightly damaged, however so far it looks otherwise to be relatively intact.
It's completely untested(again...) however I must keep my optimism that eventually I will be lucky to find the right one.

I am also talking with Alvaro who has so generously and kindly offered his 286 mainboard which is also a suitable candidate, however I am still reluctant to consider this because I am always afraid that something will happen to it, I will blame myself a lot and that is definately something I don't want to happen. I have had offers before to help me but I have discouraged them with the real possibility that a mainboard could render defective simply due to age and stress under test. It seems these discrete mainboards are delicate systems. Recently I also realized that there are so many components on the 4 layer boards that this makes the entire mainboard more sensitive to develop broken traces especially if something not so delicate happened in their lifetime, let's not forget that stuff can happen in transit too, which happened to my first ARC board. After all, I will need to do some desoldering of PALs, change the reset logic for testing etc., which is not exactly museum level preserving condition usage. The reality is, the purpose is to serve as a reference and to undergo rigorous testing and probing. A board which can stand these will be the big winner and will finally elevate my project to the circuit design level phase.

The ARC board is coming from Texas US to The Netherlands so it will take a while to arrive here. I will update as soon as I can do some work on it.
Of course I will first wash, clean and dry the mainboard, then I will remove the damaged CPU socket. I will soon need to buy a Hakko desoldering gun and a new SMD hot air gun to combine for the most perfect desoldering setup.

I am not sure yet if I can get the courage to want to try to use Alvaro's mainboard....

I am also having an IBM 5170 system on my wishlist, and would even be willing to trade my Amiga 1000 for it, for example. Recently I got that Amiga to power up and boot, and the original keyboard is only missing one key, otherwise it was working when I tested it. I know it's no guarantee of course. It's a kind of precious collector's item but for the purpose of this project, I might part with it for an IBM 5170.

I really feel (from my perspective) that with the 5150, 5160 and 5170, IBM played an essential role in computing history. I hope some day I can get a new ATX type case made, very similar to the IBM iconic desktop models. Then stack a cool CRT on top, it will look pretty cool!

I welcome and appreciate all comments, ideas and thoughts, and will post more updates on the project as soon as I can!

Kind regards,

Rodney
 
A small update, I just managed to buy what looks like an IBM 5170 type 2 mainboard, which I could not resist.
It's untested but looks complete and intact. There doesn't seem to be any visible damage to the PCB and slot connectors.
There is some wiring which is present on the top side of the PCB but I have also seen some wiring on the bottom on some photos of the same type of mainboard so I believe it was done by the factory.

Now let's hope that I am having some luck to have found a suitable candidate which is able to function as the reference for my project!
 
I am still waiting for the two reference mainboards to arrive by mail.
- ARC X286 Model 12
- IBM 5170 type 3 (62X0670)
Unfortunately the IBM is not packed very carefully, it is coming from the UK and there is only a covering of cardboard and then it was inserted into a big padded envelope, apparently with some extra padding on the corners. It is clearly indicated fragile with red tape but I doubt it will be observed.

I shudder to think what will happen when this 1,1kg envelope goes through the mail containing an IBM 5170 mainboard...
Maybe it will arive in several pieces...
I hope I can have some good luck, I will need it!

While waiting, I started to assemble the IBM schematics in Kicad.
I am getting a better insight into the structure of the AT while doing this work.
I may decide to draw up the IBM type 3 PCB with all correct placements of components which makes troubleshooting a 5170 type 3 much more easy using Kicad PCB to quickly be able to highlight and trace connections.
It also depends on if the 5170 mainboard functions and needs troubleshooting or not whether I will consider doing this work.

I also checked the PAL pins with the whole 5170 schematic to see which are inputs and outputs.
I am also thinking, if the IBM works, to probe the PAL outputs with a logic analyzer and trigger on the output activity to capture the signals around that moment.
Then the inputs which trigger the signal to become active should also provide the correct logic functions.
I could wire up a PCB with switches and LEDs to verify the functions with the original PAL.
After I know the equations I can also verify the PALs on my other mainboards.

While searching the internet, I came across a very interesting PC, the Televideo Telecat 286.
The manual contains a schematic and from this you can see their approach is slightly different.
I am even thinking it could be possibly more reliable in the long term.
I am still not sure about PAL reliability in general because I saw one mainboard die on the testbench just from a power failure.
They are using 82S153A PROM chips instead of PALs. In principle, these should also be much easier to read out than PALs.
Also it's very interesting to see that they are using sequences of flipflops to control the timing and feed the outputs back into a PROM.
Maybe this is also the approach inside chipsets.
Perhaps someone who owns one could read out their PROM chips which should be pretty straightforward.
I am not sure if their ROM code is compatible with the generic discrete AT design.
Anyway, after I am further along with the project, I may look at this Televideo schematic in more detail to find some possible parallels with this design.

I will update here when I receive the mainboards.

Kind regards,

Rodney
 
Both mainboards have arrived now. Thankfully the IBM 5170 was not damaged at all, to my pleasant surprise.

I started to work on the IBM 5170 mainboard. It's a type 3 mainboard.
I washed and cleaned the mainboard which was quite dirty. Unfortunately it was corroded from being kept in a very moist environment for a long period in the past.
I have replaced the power connector because of corrosion on the contacts.

When testing with the original IBM ROMs I saw many parity errors reported and this halted the CPU each time.
When the mainboard did boot, it loaded basic automatically, after some testing with simple basic programs it would soon give another parity error and stop each time.

I have determined that the errors don't come from faulty RAM, it's something else.
I have tested with two different batches of RAM chips, one from a know working mainboard definately without any RAM errors.
The IBM RAM sockets seem to be allright.

During my testing the RTC/CMOS chip suddenly died, probably due to bad corrosion on the legs which got into the chip.
This chip has seen so much moisture that there was even iron rust on the legs
After replacing the CMOS chip I proceeded with more testing.
I switched to the "generic 286" MR BIOS and the mainboard no longer was showing constant parity errors and I was able to test much more.
However this was not the actual solution, during RAM testing by Checkit I was getting some parity errors reported by Checkit itself, not from any BIOS messages.

So it's simply the IBM BIOS which is probably much more active in checking parity which caused the CPU to freeze more often before, making more elaborate testing pretty much impossible.

This parity problem is not consistent, there can be several good passes of Checkit full RAM test cycles completed, and then suddenly a sequence of parity errors will start to appear.

There is no consistent memory area where the errors happen, always in a different area which corresponds with the actual problem since the cause is suspected not to be the RAM itself, so it must be another component or problem. I suspect it's possibly some faulty area in the parity logic itself.

If the RAM was not being accessed properly for whatever reason, I would expect some other errors and behaviour like devide by zero stops, freezing, strange program glitches etc.
Also in normal operation the mainboard works perfectly, it can format floppy disks and boot from XT-IDE fine.
I could format a floppy and copy all files to it without issues. So normally I am not seeing any problems.

Which leads me to believe it's the parity logic throwing incorrect errorsm but only occasionally.
After listing parity errors in Checkit the mainboard never freezes but continues to function normally to complete all RAM tests.

I have a feeling that if I completely disable all parity checking, this mainboard will work perfectly.

I could proceed to desolder a lot of stuff and replace it using sockets to see if this clears the errors but because it's intermittent to happen, it's a hard fault to find, it requires around 10 minutes of testing or more each time, not ideal to trace the error quickly.
Basically if I can't measure and see the fault happening, I can only replace parts that may possibly be involved in the errors.
I will probably use a method to replace a group of ICs each time, and then let Checkit run another sequence of full tests.

If anyone knows about these random types of parity errors and knows some common fault as a possible cause, please let me know, you can save me a lot of time to trace these errors.

During tests my old AT PSU seems to sometimes not power up.
I already removed and tested all the capacitors, they are still in perfect state after around 30 years.
I checked the power rails and fine tuned the 5V.
It sometimes refuses to power on.

Anyway, I will modify another PSU with AT power wiring that is also suitable for this mainboard, where the total 12V load is not greatly influencing the 5V rails.
I have a few candidates which include a Delta powersupply of much better design.
I don't like my other modern ATX PSU because its 5V is around 4,8 volts, a bit on the low side.
This PSU is too simple in construction and needs much more current on the 12V which an old mainboard system doesn't draw.

I am considering my options, my preference is still the IBM mainboard because it's more according to standard design and there is a known full schematic.
I am recreating the schematic in Kicad for the original IBM circuits, I'm about half way through.

I noticed in this type 3 revision of the 5170 there is some modification of the ROM control logic compared to the schematic provided by IBM.

The ROM jumper block part is not populated and there are 3 connections visibly in place on the PCB layout.
This can't correspond to the normal ROM circuit sheet.
The default configuration is simply using 2x 32kb ROMs which is of course fine anyway.
I will verify this modifcation later, it's possibly combined with some changes in the memory decoder PROM.
I really only need the memory map since I will create my own SRAM/ROM decoders later.

The ARC mainboard has light battery corrosion from a battery pack which was probably mounted somewhere above the mainboard to the back of the case.
There is no distinct affected area, but certain ICs are showing some green corrosion on their legs, especially around the battery connection.

So I will be washing it, treating with acid to neutralize the battery chemicals and then I will be testing it.
The CPU socket was ruined so I will replace it from my other ARC mainboard together with that CPU chip.
Anyway, I can replace anything now I have the proper tools again.
This ARC is an older one, from early in manufacturing. It doesn't have the wires on the bottom which my previous one had.
It's a pity not the highgloss PCB type.

After I get the ARC to work I will think again about how I will proceed with the project, I will definately spend more time and effort on the IBM mainboard because of it being an IBM and matching the known schematics for the most of it.

I hope someone experienced in repairing IBM 5170 ATs could give me some advice.
The existing documentation doesn't show much about faulty parity checking issues.

Kind regards,

Rodney
 
If anyone knows about these random types of parity errors and knows some common fault as a possible cause, please let me know, you can save me a lot of time to trace these errors.
You ruled out the RAM chips.

Whilst reading the symptoms, I thought, "This sounds a bit like failed RAM refresh". At [here], you can see the varied symptoms of failed refresh on a 5150/5160 motherboard. Subsequent to writing that, I discovered that I have a 5160 motherboard that, with RAM refresh disabled, can hold RAM contents intact for between 60 and 70 seconds (consequently, the 10 second refresh test of the SuperSoft/Landmark diagnostic ROM passes).

I have a feeling that if I completely disable all parity checking, this mainboard will work perfectly.
If it doesn't, perhaps suspect the RAM refreshing mechanism.

Cassette BASIC appears to be reasonable test of RAM refreshing. Create a line of code, then do absolutely nothing (except breathing) for say, one minute, then see if a LIST command shows the line. (Cassette BASIC even may 'fall over' at the point of pressing the L key.)

After listing parity errors in Checkit the mainboard never freezes but continues to function normally to complete all RAM tests.
One thing that I expect RAM testing software to do, is to disable the CPU from receiving the NMI that results from a RAM parity error. That way, the screen will not clear and PARITY ERROR display. On an IBM 5170, the RAM testing software can see if a parity error occurred by checking chip U128 for the status of the PCK line (parity error on motherboard) or IO CH CK (parity error on ISA card).
 
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