hello
actually I was investegating my own question from post "Different types of Intel Inboard 386/pc's" - do they perform different?
But I was annoyed, not able to manage my "new" cyrix 5x86 x4, and the performance only looked like x3.
(picture of the "new" 5x86x4. There is no "x4" labeled on the chip, but the model "G5FB607B" in my case IS a "x4" cpu.
One remark, the CPU do get hot , and i have to cool it with a fan!
After some hours of testing and i found a way to enable the cache on the 5x86.
And the good and bad news is - the score from DOOM fullscreen test is now:
8621 realticks
equals 74690/8621 =
8,67 Fps !!
..the good news, the 5x86x4 were faster then the 5x86x3.
But the bad news - my prediction that the ISA-bus were the limiting factor
seems to bee non-void. My newes speedtest surpast the 7.x Fps "limmit" i tought were build in the ISA design.
I did try the LSSER and the Branch Target Buffer option - but Winstone94 did NOT like it, and all the test app's crashed.
But simple setup of 5x86 with cache enabled, works well.
The speed600 looks like this:
Discover 2.03 from Helix looks like this:
PS. Puzzle.exe runs in 2.91 secunds
the topbstub score=56.
Winstone94 gave this result:
My quickly assembled and perhaps too long procedure (but it works) :
boot IBM5150
with pcdos and Netroom3
cx5c86.exe /CD (disable cache in 5x86)
after boot finnished
run: encache.com (the tool that came with the imposter)(enable cache in imposter)
run: ET586 /SCD (disable cache)
run: ET586 /WBE (enable write back cache)
run: ET586 /CCD (equals CD=0 and NW=1)
...and the 5x86 then runs in x4 mode.
cyrix settings looks then like this (ET586.EXE /S) :
ET586 (c) 1995 by Evergreen Technologies, Inc. (11/28/95)
Version 1.1 (Release Version)
586 Configuration Register Dump
REGISTER INDEX BITS 7 6 5 4 3 2 1 0 = Hex
-------- ----- --- --- --- --- --- --- --- --- -----
PCR0 20h 0 0 0 0 0 0 0 0 00h
CCR1 C1h 0 0 0 0 0 0 0 0 00h
CCR2 C2h 0 0 0 0 0 0 1 0 02h
CCR3 C3h 0 0 0 1 0 0 0 0 10h
CCR4 E8h 0 0 0 0 0 1 0 1 05h
SMAR0 CDh 0 0 0 0 0 0 0 0 00h
SMAR1 CEh 0 0 0 0 0 0 0 0 00h
SMAR2 CFh 0 0 0 0 0 0 0 0 00h
PMR F0h 0 0 0 0 0 0 1 0 02h
DIR0 FEh 0 0 1 0 1 1 0 0 2Ch
DIR1 FFh 0 0 0 0 0 1 0 1 05h
MSW (CR0) = A0000011
NW Bit = 1
CD Bit = 0
and thanks to forum member feipoa for answering technical questions.
/cimonvg