Hugo Holden
Veteran Member
Eudi said:
For instance, the 40 column PET (the ones with "hardwired" video pre-dating the CRTC-equipped ones) demonstrates a way to do it. TL;DR, it essentially breaks display memory into 8 byte pages that are incremented directly and "recirculates" the higher address bits through a latch that preloads the counters at the start of the active area of each line. For an 80 column screen you could duplicate this *almost* exactly; just move the addressing over 1 bit to use 16 byte pages.
It is an interesting recirculating circuit, even impressive drawn on paper because it is a loop. In these cases it is a good thing that gates, flip flops etc have a data transmission delay, so the input data stays stable enough to be used, before it changes to a new value later after a change in state.
Though data latches help, and if a two phase clock is used, breaks up what amounts to read and write states into separate temporal events.
One of the more simple examples of a logic loop like this, is the D type flip flop, to get it to toggle you can connect its /Q output into its D input and usually, the data at the D input stays stable long enough for it to toggle reliably on each clock pulse. One way you can make it ignore multiple transitions on a clock signal (say from a poorly de-bounced switch) is to put an RC delay (or a logic gate delay) in the /Q to D link. Still, making a toggling flip flop this way is not nearly as reliable as using a JK flip flop with both J&K held high. The D flip flop wired to toggle with this short loop can sometimes give trouble near the high frequency end of the logic family's operating range.
For instance, the 40 column PET (the ones with "hardwired" video pre-dating the CRTC-equipped ones) demonstrates a way to do it. TL;DR, it essentially breaks display memory into 8 byte pages that are incremented directly and "recirculates" the higher address bits through a latch that preloads the counters at the start of the active area of each line. For an 80 column screen you could duplicate this *almost* exactly; just move the addressing over 1 bit to use 16 byte pages.
It is an interesting recirculating circuit, even impressive drawn on paper because it is a loop. In these cases it is a good thing that gates, flip flops etc have a data transmission delay, so the input data stays stable enough to be used, before it changes to a new value later after a change in state.
Though data latches help, and if a two phase clock is used, breaks up what amounts to read and write states into separate temporal events.
One of the more simple examples of a logic loop like this, is the D type flip flop, to get it to toggle you can connect its /Q output into its D input and usually, the data at the D input stays stable long enough for it to toggle reliably on each clock pulse. One way you can make it ignore multiple transitions on a clock signal (say from a poorly de-bounced switch) is to put an RC delay (or a logic gate delay) in the /Q to D link. Still, making a toggling flip flop this way is not nearly as reliable as using a JK flip flop with both J&K held high. The D flip flop wired to toggle with this short loop can sometimes give trouble near the high frequency end of the logic family's operating range.
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