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Time to rebulid the pdp8/L

czunit said:
Ok, thanks! Flip chip is a bit maddening, for example the single side boards (much of the G logic) only have pins on one side, which is the solder side. Is there a version of the Logic guide that explains exactly what pin is what? Does the lettering order flip as well if it's a single side vs. double side board? Ug.
Click to expand...

It's all meant to read intuitively from the wire-wrap side of the back-plane.

Single sided cards were just enumerated "A" through "V". Double sided cards added the "1" and "2". Everything counts up, if you look at it from the back-plane side with the correct orientation. (If you mentally add a "2" to the single-sided modules' pin numbers,) On an 8/L, that's even the "top" :).

The modules themselves are numbered in a similar scheme, with A01 in the upper left corner. Then one can find pin B08K2 by counting down for the letters and right for the numbers. As you've noted, this is not intuitive at all from the front or top side views of the modules.

Hope this helps.

Vince

(Done from memory, but hopefully I got the details right.)
 
Much appreciated. This plus my sitting down with a card, the schematic, and a tester and I have the lettering down pat :)

Re-checked from the back: K2,L2,M2,N2 are all high. P2 (output) is reading high. Note K,L,M are powered by a resistor divider network on the card, my guess is the M617 is a higher power gate that will clock the 12 flip flop loads. Note also that the 617 is fed by a M111 (inverter) in D2 which is then fed by one of the M360's (delays). That's why it is on the instructions as a inverted MB signal. The NAND just re-inverts the signal but amplifies it.

Note: If the 617 is not in there and the M111 in D2 is out, then the output P2 will be 1.4 volts if any of the M220's are in there. I think this is because when there isn't a ground or hot signal on these 7400 components they float to a third state.

Found that the M617 was bad (always high on MB) but replacing M617 on slot B8 has resulted in some very odd things. First, the M617 is asserting low when all inputs are high which is what it should do. Second and far weirder:

Loading a memory address with Load ADDR is loading the address, but if you click load addr again it decrements the address in the memory address register.

That is very, very weird.Examine and deposit do an addition to the address (no data in the MB) but it's like Load address is decrementing the address after the first click. It even wraps around if you put 7777 into the memory address. Weird!

Something else is very stuck. I think I have a number of elements here that are doing very odd things. Plus if stuff is not grounded or hot the states are indeterminate, which is bad.

Time to start over from the beginning but document everything. At least I found a failed NAND gate. Now to re-check the other lines to the M220's, maybe another one is stuck and causing the MA to somehow hit a subtraction element.

Weird. At least examine and deposit increment the register properly (though the memory buffer is still empty). Wonder if there is a problem with the M360's.
 
czunit said:
Loading a memory address with Load ADDR is loading the address, but if you click load addr again it decrements the address in the memory address register.

That is very, very weird.Examine and deposit do an addition to the address (no data in the MB) but it's like Load address is decrementing the address after the first click. It even wraps around if you put 7777 into the memory address. Weird!
Click to expand...

The increment that is intended is done using the adder of the M220s. A decrement instead suggests that the operand that's getting added is somhow 7777 instead of 0001. Or maybe the wrong function was selected for the ALU chips?

Something else is very stuck. I think I have a number of elements here that are doing very odd things. Plus if stuff is not grounded or hot the states are indeterminate, which is bad.
Click to expand...

That is odd. Undriven TTL inputs should float high.

Vince
 
I'm not sure about the PDP-8/L but pressing Load Address multiple times on the PDP-8/E just reloads the memory address register with the contents of the switch register. Nothing should be incremented or decremented.
 
Load Address should load what is in the front panel switches. Nothing should be added or subtracted at previously stated above.
 
BitWiz said:
I'm not sure about the PDP-8/L but pressing Load Address multiple times on the PDP-8/E just reloads the memory address register with the contents of the switch register. Nothing should be incremented or decremented.
Click to expand...

Yes. I assumed he meant he was pressing EXAM repeatedly, and it was counting the wrong way.

Vince
 
Nope, load address *is* decrementing the MA register. Super weird. Exam/Dep increment the register.

The 617's are fine logic-wise. Something else is up, will check one of the M220's tomorrow and see what's going on.
 
That is really weird. It's almost like it's treating Load Address as Examine/Deposit but decrementing. Somehow one of the M220's must have a latch set wrong or something like that.
 
That's probably it: The blown card was probably masking another problem. Oh well, back to stage 1 for testing, then find the next problem, then...
 
Ok, fixed the load address issue. What a mess.

To make a very long story short, the system almost seemed as if it was halfway running. Removing the 310's was changing the behavior, which didn't make sense. Finally I swapped the M216 (6 flip flops) in C4 and the system went back to handling the load address key properly. So at least I can load the memory buffer. It doesn't increment or decrement on load address anymore (it just.... loads the address), but it does properly increment when doing dep/exam.

So it's getting a bit better.

C4 looks important, it seems to tell the computer if it's in state 1,2,3,4, pause, or memory idle. If it's stuck in a state when it's supposed to be idle then yeah who knows what is happening...

Anyway.... Back to the drawing board figuring out why the MB isn't working. What's a good way to bench test flip flops? I now see there is another M216 that controls memory enable, read, write, cycle, inhibit, and lock.

Maybe I should just replace all the flip flop chips with new ones. Bad idea?

Score: 1 dead 8 input NAND gate, stuck on
1 dead set of flip flops.
 
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czunit said:
Anyway.... Back to the drawing board figuring out why the MB isn't working. What's a good way to bench test flip flops? I now see there is another M216 that controls memory enable, read, write, cycle, inhibit, and lock.
Click to expand...

I don't know your location, but it is possible there's someone with a flip chip tester near you. They are really helpful and in an afternoon you can go through an entire 8/L sized back-plane pretty easily and at least identify modules that are obviously broken.

Vince

(Unfortunately, I don't have any stock at the moment to sell you a kit.)
 
Replacing the 7474 flip flops is really not that hard: DEC did of course bend a pin on each one so you have to straighten that out but since I have a soldering iron and air tools it's not that bad: Simply clean the pins, put flux on desoldering braid, fire up the iron on low heat (this is not that ROHS solder junk) and take off the solder. Then put a jeweler's screwdriver under the chip, turn on the air heat, and warm the desoldered board till the chip pops off. Not too much heat or you will brown the board (yeah it's a single layer board so who cares but aesthetics). Then clean up with isopropyl, put the new chip in, and quick solder it in place.

Maybe I should just replace all the M216's. There is also a flip flop over on the M700 and that is a very major memory component. Hm.
 
vrs42 said:
I don't know your location, but it is possible there's someone with a flip chip tester near you. They are really helpful and in an afternoon you can go through an entire 8/L sized back-plane pretty easily and at least identify modules that are obviously broken.
Click to expand...

That would be a great thing, but I don't know anyone off the top of my head.

However I'm going to try cheating a bit: I just ordered a 7400 series chip tester and a 16 pin chip clip. Since most of these boards have all the gates going to the pins (instead of chaining, etc) I should be able to just clip onto each chip and run the logic tests. Granted it won't test the transistors (probably good) or complex things like the delays, but at least it will check the NAND gates, buffers, and the flip flops. That would be a large head start...

C
 
New day, and while I wait for the logic tester to arrive I thought I'd do some thinking about why nothing works in the memory. Going to the state design document they have a nice flowchart about what happens when you press buttons. For example: The Load address button does the following:

MFT0: Sets the major state registers to 0 (this seems to happen)
MFT1: Moves the switch register to the memory address (this happens)
MFT2: Moves the switch register to the program counter (this happens)
Does a MEM START (This happens)
T2: Nothing
T3: Moves 0 to run (stops the processor) This I think happens.

Now for examine or deposit this happens:
MFT0: 0 to major states. This seems to happen again
MFT1: PC goes to memory address (This seems to happen)
MFT2: MA+1 goes go PC (this happens, it's how it increments the address)
Does a MEM START (This happens)
T2: If Examine move MEM to MB (which should display, doesn't happen)
If Deposit move SR to MB (which should also display doesn't happen)

So maybe either MEM_START never happens and the chain is broken or T2 is never cycling. I'll start checking to see what fires off T2 cycle and what the MEM Start cycle is. Maybe it's another bad flip flop.

Edit: So I put the M113 in C2 up on the riser. I can see a pulse coming out of when either examine or deposit is toggled, so the MEM_START signal does exist. I don't know what that triggers, but it at least is happening. What does MEM_Start pulse do?

What is interesting is in the write up they refer to a MFT3 which moves things from the SR to the MB register on a deposit. Maybe the MFT3 cycle isn't happening and I wonder if that's the same as the T2 cycle on the schematic flow diagram.

Hm. Either way I wonder if the problem is something is stuck in MFT3/T2....
 
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Do you have access to a logic analyzer? You could hook up multiple probes to different signals to see what's happening. Or is this what you are already doing?
 
czunit said:
Edit: So I put the M113 in C2 up on the riser. I can see a pulse coming out of when either examine or deposit is toggled, so the MEM_START signal does exist. I don't know what that triggers, but it at least is happening. What does MEM_Start pulse do?

What is interesting is in the write up they refer to a MFT3 which moves things from the SR to the MB register on a deposit. Maybe the MFT3 cycle isn't happening and I wonder if that's the same as the T2 cycle on the schematic flow diagram.
Click to expand...

MEM_START signals the core memory timing chain to begin. This essentially starts a core read-modify-write cycle. The memory should proceed (at it's own, self-timed pace) to read out the core specified by MA, loading it into MB. This has the side effect of erasing the word. There's a brief pause, during which the CPU can modify MB (presubably meant to coincide with MFT3 above). Then the contents of MB will be written back to memory.

At the MEM_DONE time, the CPU will check RUN state to determine whether to keep going or to stop waiting for the front panel.

Vince
 
MEM_START signals the core memory timing chain to begin. This essentially starts a core read-modify-write cycle. The memory should proceed (at it's own, self-timed pace) to read out the core specified by MA, loading it into MB. This has the side effect of erasing the word. There's a brief pause, during which the CPU can modify MB (presubably meant to coincide with MFT3 above). Then the contents of MB will be written back to memory.

At the MEM_DONE time, the CPU will check RUN state to determine whether to keep going or to stop waiting for the front panel.

Vince
Click to expand...

Ok. If I might ask, what does the MEM_START signal tickle in terms of which board/circuit path? It seems to get to the point where it tickles mem start, but nothing comes back to the memory buffer. Or to be more accurate the MB is all ones and never clears (the system starts up with pretty much all ones in all registers when turned on. Clicking load address sets the address, and clicking exam or dep clears the accumulator but nothing clears the MB). Does it set a flip flop somewhere that starts a signal through the 4 M310's for the memory cycle?

I see that the M700 is a "manual timing generator" where time states are generated off a signal passing through 4 transistors. Is this the timing system used for commands like load address and load/exam data?

On a lark I did try switching the inhibit drivers, but no progress there.

This has got to be something really simple. Hm.
 
tradde said:
Do you have access to a logic analyzer? You could hook up multiple probes to different signals to see what's happening. Or is this what you are already doing?
Click to expand...

Unfortunately no. I suppose I could drag out the scope and take a look at two signals at once, that could be the next step.Right now I can see evidence of a signal by watching the subtle voltage change on the Fluke meter.
 
czunit said:
Ok. If I might ask, what does the MEM_START signal tickle in terms of which board/circuit path? It seems to get to the point where it tickles mem start, but nothing comes back to the memory buffer. Or to be more accurate the MB is all ones and never clears (the system starts up with pretty much all ones in all registers when turned on. Clicking load address sets the address, and clicking exam or dep clears the accumulator but nothing clears the MB). Does it set a flip flop somewhere that starts a signal through the 4 M310's for the memory cycle?
Click to expand...

On sheet D-BS-8L-0-13, you'll find where MEM_START sets MEM_ENABLE, and also starts a series of M310 delay lines running to control memory timing.

Vince
 
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