| VCF Latam | Apr 24 - 26, 2026, | Bahía Blanca, Argentina |
| VCF Pac. NW | May 02 - 03, 2026, | Tukwila, WA |
| VCF Southwest | May 29 - 31, 2026, | Westin Dallas Fort Worth Airport |
| VCF Southeast | Aug 01 - 02, 2026, | Atlanta, GA |
| VCF West | Aug 01 - 02, 2026, | Mountain View, CA |
| VCF Midwest | Sep 12 - 13, 2026, | Schaumburg Convention Center, IL |
| VCF Montreal V2.0 | Nov 07 - 08, 2026, | Saint-Lambert, Montreal, Canada |
| VCF SoCal | See you in 2027, | Southern CA |
| VCF East | Apr TBD, 2027, | InfoAge, Wall, NJ |

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D 0x44 vs ox64 = 0100 0100 vs 0110 0100 = Bit 5 Different
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S 0x53 vs 0x73 = 0101 0011 vs 0111 0011 = Bit 5 Different
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Y 0x59 vs 0x79 = 0101 1001 vs 0111 1001 = Bit 5 Different
CRT 8002 & 5037
The 8002 Video (Character) Generator LSI and the 5037
Video/Timer Controller LSI make up the majority of the
video section. The 8002 contains a predetermined character
set, 128 alphanumeric characters and graphic symbols. When
a character is to be output to the CRT, the address of the
character is placed on the address bus of the 8002 by the
microprocessor. When the 8002 is selected, this character
address is input to the 8002. Then, in time with the video
dot clock, the character selected is output in serial fashion
to the CRT.
The only attribute selection used by the Eagle system is
reverse video. When reverse video is selected, the reverse
video line is pulled high and the character data is inverted,
before it is placed in the serial output shift register of
the 8002.
The other part of the video section is the 5037. This LSI
is not pre-programmed. It is programmed with seven 8-bit
words that define for the 5037 the horizontal and vertical
format of the CRT display. This information is stored in
the 2732A Boot EPROM, and loaded as part of the initial
loading sequence. The information includes the size of the
display, the size and spacing of the character blocks, and
the vertical and horizontal scan rate. The 5037 also provides
the cursor mode information to the 8002.
VIDEO DISPLAY
A register at port 31H holds the cursor column position
in bits 0 through 6, and a register at port 32H holds the
cursor line number in bits 0 through 5. The bits in these
registers are used to address the 80*24 video buffer.
READY is located at port 30H, bit 7. When this bit flag
is set true a byte of data may be written here. At port 33H
is the register which is used to write data to the video
buffer.
The video controller chip is an SMC CRT5037 and occupies
a 16 byte port block which begins at port 80H.
(See Figure 16.)