• Please review our updated Terms and Rules here

Z80 speed

danielbooneamerica

danielbooneamerica

Experienced Member
Joined
Mar 2, 2020
Messages
408
Location
Wayne National Forest
Roy Soltoff once said to me that main reason for xlr8 was additional RAM.

If it were speed only the user wanted, there were Z80s faster than 64180. I have been looking around and fastest chip I see for Z80 is 10 Mhz made by Zilog.

For a real Z80, does this sound like fastest chip? I did read a rumor of a 20 Mhz but have been unable to find this chip.

Thanks

Daniel
 
The Z84C0020 is a 20MHz Z80 available in DIP-40, PLCC-44 & QFP-44 footprints.

Rather than the original 64180, there is the Z180 available in speeds up to 33MHz (Z8S18033*) and it's approximately 12% faster than a Z80 at the same MHz on the benchmarks I've tried. For even faster speeds there's the eZ80 at 50MHz which has reduced instruction cycles and pipelining which yields about the equivalent of a 160-200MHz Z80 depending upon instruction mix.
 
WSM said:
The Z84C0020 is a 20MHz Z80 available in DIP-40, PLCC-44 & QFP-44 footprints.

Rather than the original 64180, there is the Z180 available in speeds up to 33MHz (Z8S18033*) and it's approximately 12% faster than a Z80 at the same MHz on the benchmarks I've tried. For even faster speeds there's the eZ80 at 50MHz which has reduced instruction cycles and pipelining which yields about the equivalent of a 160-200MHz Z80 depending upon instruction mix.
Click to expand...

Yes, I had excluded eZ80 and other because they are not 100% binary compatible. I am not sure but I think Z180 is binary compatible per Zilog.
 
I think the big issue with the eZ80 is less that it's not strictly binary incompatible, it's that its internal I/O stomps on top of the addresses used by the TRS-80 and isn't relocate-able. The Z180 also has built-in I/O but my vague recollection is it all resides starting at ports 0x00h, which doesn't conflict with the TRS-80's internal hardware. (It might conflict with some devices that connect externally.)
 
Eudimorphodon said:
I think the big issue with the eZ80 is less that it's not strictly binary incompatible, it's that its internal I/O stomps on top of the addresses used by the TRS-80 and isn't relocate-able. The Z180 also has built-in I/O but my vague recollection is it all resides starting at ports 0x00h, which doesn't conflict with the TRS-80's internal hardware. (It might conflict with some devices that connect externally.)
Click to expand...

undocumented instruction binary compatibility was not maintained.

Normally that should not be a problem but sometimes you will find it used especially in older code.

Yes, for Z180 and eZ80 alike, any added I/O would not be strictly binary compatible since Z80 had none. No matter where they located it, someone would have a conflict. Best would be to allow user to relocate onboard I/O.
 
Eudimorphodon said:
I think the big issue with the eZ80 is less that it's not strictly binary incompatible, it's that its internal I/O stomps on top of the addresses used by the TRS-80 and isn't relocate-able.
Click to expand...

Speaking from the point of view of having a little bit of experience with the eZ80, this is indeed the greatest obstacle; there are ways of forcing addressing external-to-the-chip I/O ports, but if you want to output a 0 to an external-to-the-chip port you can't use the straight OUT instruction. The total lack of DRAM refresh also makes it less than ideal for a Z80 replacement.

The Z180 also has built-in I/O but my vague recollection is it all resides starting at ports 0x00h, which doesn't conflict with the TRS-80's internal hardware. (It might conflict with some devices that connect externally.)
Click to expand...

HD64180/Z80180/Z8S180 can have their internal device addresses set to one of a few starting addresses, but otherwise you have to do special magic to address off chip I/O in that range (special magic = make sure A<>0 for IN/OUT instructions using A, and B<>0 for I/O instructions using C register indirect).

And even though I have a soft spot in my heart for the grand old Z800/Z280, the fact is, other than the lack of RAS-only row-address-counter DRAM refresh of the Z80 and '180, the ultimate Z80 with the most compatibility is the current production ( https://www.digikey.com/en/products/detail/zilog/Z8038018FSG/928902 ) 16/32 bit Z380 MPU @ 18MHz, like these:

Z80380-lro.jpg

Yeah, Z380 can address 4GB of RAM, although at 18MHz you probably wouldn't want to. Highly efficient, almost as efficient as eZ80, but tops out at 18MHz to eZ80's 50MHz. But, Z380 is currently stocked and is an active item in Zilog's catalog. It's a CPU only, so no on-chip peripherals to speak of. I wish I had time to put together a Z380 system with my hand-soldered sample you see in the photo; Real Life (TM) prevents much of that for me right now. Maybe one day; I have four chips, two not soldered to carriers, and some schematics drawn. Likewise the eZ80; I have the beginnings of an eZ80 with VGA output and PS/2 input built on the Zilog modules, a hand-wired interposer, and an Altera DE1 FPGA board. Maybe one day I'll get enough time to finish it.
 
Zilog specifications were very conservative. I routinely overclocked Zilog parts and found surprises.

I've designed rev 1.3 of ZRCC with fast RAM to check out overclocked Z80, https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zrcc:zrcc1_3

The fastest Z80 is 33MHz, it takes 24 minutes to complete zexall.com under CP/M2.2

Bill

PS, I have a Z280 on my desk right now driving a VGA text display and the oscillator is 35.96MHz or 17.98MHz CPU clock (the rated CPU clock is 12.5MHz).
 
But if I read correctly some instructions on Z180 were removed such as halt, IM 0 etc. So in a pure definition it is not binary compatible.

That leaves only Z80 line that is 100% compatible. I am guessing 33 Mhz version did not change anything as far as instructions go.
 
I agree with lowen that the Zilog Z180 family impliments all of the documented Z80 instructions and it also added 12 new ones: SLP, MLT, IN0, OUT0, OTIM, OTIMR, OTDM, OTDMR, TSTIO and TST (3 variants). There are no instruction differences within the Z180 series (i.e. Z80180, Z8S180, Z8L180 etc.) although some have different internal I/O registers and react slightly differently to low power modes. They all use the same User Manual which describes the instructions.

It's my understanding that there are rarely encountered differences between the Z80 and Z180 in RLD, RRD and DAA after a DEC instruction but I've never encountered any issues with this.

Personal opinion: After writing assembler code for a variety of architectures over a 50 year span, I consider it extremely poor programming practice to use undocumented instructions. There is absolutely no reason why a manufacturer shouldn't change undocumented behaviour with different mask or microcode versions of an identically named processor. Moreover, it's my preference that undocumented instructions result in an exception event as it does with the Z180 TRAP.
 
WSM said:
I agree with lowen that the Zilog Z180 family impliments all of the documented Z80 instructions and it also added 12 new ones: SLP, MLT, IN0, OUT0, OTIM, OTIMR, OTDM, OTDMR, TSTIO and TST (3 variants). There are no instruction differences within the Z180 series (i.e. Z80180, Z8S180, Z8L180 etc.) although some have different internal I/O registers and react slightly differently to low power modes. They all use the same User Manual which describes the instructions.

It's my understanding that there are rarely encountered differences between the Z80 and Z180 in RLD, RRD and DAA after a DEC instruction but I've never encountered any issues with this.

Personal opinion: After writing assembler code for a variety of architectures over a 50 year span, I consider it extremely poor programming practice to use undocumented instructions. There is absolutely no reason why a manufacturer shouldn't change undocumented behaviour with different mask or microcode versions of an identically named processor. Moreover, it's my preference that undocumented instructions result in an exception event as it does with the Z180 TRAP.
Click to expand...

Sadly there is lots of older software and especially games that did use undocumented instructions.

With research some of this might be able to be patched and fixed. But many of them thought they would do.some stealth manuver that would help protect their code from being reverse engineered.

Some undocumented were left over from beginning roots of Z80 and some early Z80 programmers had favorite old instructions that were only retained as undocumented.
 
The FPGA Z80 core I've thought about trying out is Monte's Y80 core from his book "Microprocessor Design Using Verilog HDL" available on Amazon. If you don't know who Monte Dalrymple is, here's his resume: http://www.systemyde.com/resume.html. (in other words, he knows because he designed a bunch of this stuff at Zilog and for Rabbit).

There is a Y80e open core that implements the non-ADL eZ80 instructions; Y80 is highly efficient.
 
So what do you think? A 4 Mhz Z80 as installed in a M4 does on a good second, a little over 1 MIPS, after accounting for wait states etc.

Of course this heavily depends on the instructions but just an average guess. But I would guess well over 1 MIPS and less than 2 MIPS?
 
The *fastest* Z80 instructions take a minimum of four "T cycles", or clock ticks, with *zero* wait states. So a Z80 at 4mhz running nothing but NOPs could be said to be running at "1 MIPS". No faster.
 
lowen said:
Speaking from the point of view of having a little bit of experience with the eZ80, this is indeed the greatest obstacle; there are ways of forcing addressing external-to-the-chip I/O ports, but if you want to output a 0 to an external-to-the-chip port you can't use the straight OUT instruction. The total lack of DRAM refresh also makes it less than ideal for a Z80 replacement.



HD64180/Z80180/Z8S180 can have their internal device addresses set to one of a few starting addresses, but otherwise you have to do special magic to address off chip I/O in that range (special magic = make sure A<>0 for IN/OUT instructions using A, and B<>0 for I/O instructions using C register indirect).

And even though I have a soft spot in my heart for the grand old Z800/Z280, the fact is, other than the lack of RAS-only row-address-counter DRAM refresh of the Z80 and '180, the ultimate Z80 with the most compatibility is the current production ( https://www.digikey.com/en/products/detail/zilog/Z8038018FSG/928902 ) 16/32 bit Z380 MPU @ 18MHz, like these:

View attachment 1037672

Yeah, Z380 can address 4GB of RAM, although at 18MHz you probably wouldn't want to. Highly efficient, almost as efficient as eZ80, but tops out at 18MHz to eZ80's 50MHz. But, Z380 is currently stocked and is an active item in Zilog's catalog. It's a CPU only, so no on-chip peripherals to speak of. I wish I had time to put together a Z380 system with my hand-soldered sample you see in the photo; Real Life (TM) prevents much of that for me right now. Maybe one day; I have four chips, two not soldered to carriers, and some schematics drawn. Likewise the eZ80; I have the beginnings of an eZ80 with VGA output and PS/2 input built on the Zilog modules, a hand-wired interposer, and an Altera DE1 FPGA board. Maybe one day I'll get enough time to finish it.
Click to expand...
I was unaware this specific version of the chip supports the PC ISA bus, who knows a PC AT bus CPU card might be nice.
 
You must log in or register to reply here.
Back
Top