Thanks for the vote of confidence
.
Sorry to be quiet for a few days - I was finishing off my vacation in New York and was flying back to the UK on Thursday evening. I am now just recovering from the jet lag!
To sum up:
It seems to be a good idea to provide an add-on 6809 board for the Commodore PET to turn it into a SuperPET.
Yep - the ACIA wasn't extensively used by the community (only as a link to a 'host' mainframe computer) but I am sure there are a couple of programs out there that use it (but I don't think it a valuable add-on for this exercise).
I am preferring to use 2 off 32K*8 SRAM chips to one 64K*8 chip. This makes the PCB slightly more complex - but the 32K*8 device is widely available and cheap and could be substituted if the supplier I used decided not to produce them anymore.
I am looking at the following:
1 off 40pin DIL header (for connection in place of the PET's 6502 CPU).
1 off Western Design Centre W65C02S6TPG-14 as the 6502 CPU (this supports a BE pin to disable the address/data and R/notW line in a similar manner to the 6809E's TSC, uses a single PHI2 clock and is readily available at a reasonable price from a UK/USA stockist).
1 off S6809EP CPU (stocks of this exist within a major UK distributor from AMI (American Microsystems Inc - now ONSEMI) so I am reasonably confident that these devices are not fakes or counterfeits and are a reasonable price).
2 off 32K*8 CMOS SRAMS.
1 off 27C256 32K*8 EPROM (or an equivalent EEPROM).
I will try and design the circuit to accommodate different manufacturers devices for the SRAM and (E)EPROM to keep our options open for future obsolescence.
I will have to generate a clock for the S6809EP (Q and E pins). I don't particularly like the circuits used in either the 1 or 2 board SuperPET as they seem to contain design errors. I am, therefore, planning to use the clock generator circuit from the 6809E data sheet (a 74LS76 and 1/6 74LS04 with an additional pull-up resistor). Unfortunately, this means that I will need a 4 MHz 'flying-lead' from the PET master timing circuit. Let me think about this one a bit more...
The 74LS123 (U12) will remain for the CPU changeover reset logic.
I can't justify the 'NOP generator' to myself (I only have the hobbyist copy of Eagle so 160x100 mm is the maximum size of the PCB I can design - and I tend to space out my components quite a lot rather than cram then in). Can you persuade me Dave?
Quite happy to entertain the on-board switches to select 6502/6809/PROG and RO/RW/PROG - but can you give me a little more detail why you think they would be useful? I would have thought most people would want a 6502/6809 switchable solution and the RO switch option is not much use hard-wired on its own.
I agree with the 'non-PAL' solution - but I may run into PCB design constraints if I don't use a PAL (due to the large number of 'glue' devices) if I am not careful. I have an 'aged' GAL 16x8 and 22x10 programmer which I would like to upgrade anyhow. I can't see these devices becoming obsolete for a fair while. I notice Lattice have stopped doing them - but ATMEL have picked up the range and extended it I see. I suspect my programmer won't program ATMEL devices though... I have the software to produce the JEDEC file from the logic equations though.
Incidentally, using the W65C02 means that I potentially don't need the horrid switchable 5V supply (I can keep the 6502 CPU powered all the time) and, therefore, that I don't need the +9V unregulated supply (just the regulated +5V supply is all I need if I ignore the serial converters - another reason for not incorporating the ACIA).
The use of low-power parts (as far as practicable (e.g. CMOS SRAM and (E)PROM) and the much reduced 'glue' logic should mean that I can use the regulated +5V supply from the PET 6502 CPU pins...
Unless anyone has any concerns with what I have written above, I will wire-wrap up my prototype design (bringing the 'control' signals out to a header for now) and then start to think about the PAL logic in parallel.
I also plan to add a RESET switch to the PCB if anyone wants to fit it.
I will ignore U45 and U46 (as these were used as additional ROM sockets for the 6502 if my memory serves me correctly), and 'compress' the software that occupied U47, U48 and U49 into my single EPROM (mapped from $A000 to $FFFF in the 6809 address space). I will still need a modified character generator for the PET to access the additional characters that the SuperPET required (e.g. the APL character set).
There are a couple of issues that I am confused by at the moment:
1. Under what circumstance is the DIAG bit (U35/3) of any use? I know it causes the 6502 PET to enter the debug monitor when activated - but I can't think of any use in 6809 mode.
2. I/O port $EFFE data bit 0 seems to swap RAM for ROM. Do I need to implement this for the 6809? I don't think so and, therefore, U37 can be omitted.
3. U37 data bit 7 (memory map register) seems to be used to enable/disable the clock for U35 on the combined SuperPET board. It doesn't seem to be wired on the 2-board set. If this is the case, then the software should not use this bit and I can omit it.
It's midnight in the UK so I think I had better go to bed before I fall to sleep at the keyboard!!!
Cheers,
Dave