I've revisited the idea of having 40-pin and CF on the same card - here's the result. The board has master/slave CF config, switchable pin-20 VCC (for DoM power), won't support IRQ or DMA based operation, but the CPLD has the necessary connections to support code providing functionality of the original XT/IDE, 'Chuck-mod' (enhanced read) and also any future memory-mapped IO.
With this size board it's pretty tricky; there just isn't enough room to make it work without some highly dubious routing. Attached a design - any comments on these would be very gratefully received. Main problem is that traces run very close together, and to e.g. CF mounting holes, and right to the top edge of the board. Someone with more experience could do a better job with it I'm sure.
In particular, a second pair of eyes on the schematic would be great (edit - I've picked up missing ground connection on CF-CSEL DIP switch already, just not updated the ZIP file). CF slot is first-in-line, then routed on to the 40-pin header. PDIAG and IOCS16 are linked between CF slot and 40-pin header, 40-pin header also has DMARQ with 5.6k PD. None of those go back to the CPLD.
Do we need B8 (/nows) hooked up? According to the PC/XT technical reference it's not defined on the XT anyway (listed as reserved).
Design pack here.
Re PC/XT slot 8, I can't answer that. The technical reference describes the signals on JP8 preceded with an X, i.e. XD0 as opposed to D0 (page 1-45). Re SMT, minimum run for professionally assembled boards is qty 100 I think, but I just don't have the capital available to fund that.