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PDP 11/45, Part 4

Hi All;

Thank You, Don for Your Amazing Insight.. And so coming thru again..

Just what the Doctor Ordered, AMA (American Medical Association) is enabled..

And so it fixed our problem, I will try it out Tomorrow.. Thank You for Your Help..

THANK YOU Marty
 
Hi All;

Thank You again, Don..

That fixed the problem.. No warnings or other problems..

GSD:
MODNAME =0 flags=0
PSECT =0 flags=40
PSECT . ABS.=17412 flags=104
XFER . ABS.=1 flags=10
ENDGSD
RLD
Location counter definition . ABS.+17300
TEXT ADDR=17300 LEN=112
017300: 023727 017406 017300 103401 .'......
017310: 000000 000772 023737 017410 .....'..
017320: 017406 103402 000000 000764 ........
017330: 013703 017406 000401 005713 ........
017340: 010313 005703 001403 020337 .......
017350: 017410 101371 000240 020313 .......
017360: 001007 020337 017406 103402 ... ....
017370: 000240 000742 005723 000766 ........
017400: 010300 000000 000766 017276 ........
017410: 000200 ..
ENDMOD

I Corrected a couple of Mistakes in the program, from the original.. After comparing the codes from each..
Here is the Corrected Program..

;BASIC ADDRESS TEST (DOWN)
;COPYRIGHT 1970, DIGITIAL EQUIPMENT CORP •• MAYNARD, MASS.

NOP=000240
.enabl ama
.asect
.=017300

STCK: CMP STADD,#STCK
BLO .+6
HALT
BR STCK
CMP LODOWN,STADD
BLO BEGTST
HALT
BR STCK
BEGTST: MOV STADD,%3
BR .+4
DWNTST: TST -(3)
MOV %3,@%3
TST %3
BEQ READUP
CMP %3,LODOWN
BHI DWNTST
READUP: NOP
CMP %3,@%3
BNE ERROR
CTINUE: CMP %3,STADD
BLO INCRM
NOP
BR STCK
INCRM: TST (3)+
BR READUP
ERROR: MOV %3,%0
HALT
BR CTINUE
STADD: STCK-2
LODOWN: 200

.END

And it Loads and Runs on the Real PDP 11/45..

Next I am working on the program -- MAINDEC*DCKBH-A ALL PDP11/45 REGISTERS..

I have the whole program typed in, but for some reason, when I try to assemble it with macro11, it doesn't come back to the prompt, I have waited for a full five minutes.. And no action from the program, Is there an upper limit to the length of the program ??

I Found the problem, I had Three Typing Mistakes, that brought down the whole thing.. In each case I had forgotten to put a MOV in front of the rest of the program line..

So it Assembles fine, I am going to next try and Run it on Simh, I will let everyone know what happens..
Well, I don't know, the program is Supposed to Ring the Bell, But since I Don't know How to make TeraTerm or something like it work with Simh, it can't ring the Bell..
Is there a way to hook TeraTem and Simh together ?? (For a Serial Output)..

I Loaded it on the Real PDP 11/45, and it faults at Test T4, Now at this point, I have no way to verify that it actually Ran on Simh, and that the CODE is Correct..
I found three mistakes, and some of the time the Printing on the Listing was not very good, So there could be a problem there, between my Interpretation of what I though I saw and what was really there in the Listing..

I made some changes, in the Code for T4 and T5, which I will Test in the Morning on the Real 11/45.. And see if it better, the same or worse.. It is one of those areas that it could be a couple of things and I need to check it out, by trying it on the real machine..

I finally got things to run on Simh, If I go past the initial code, which just does it's own looping, and start at the actual Tests, then I get a Failure at T3, which is good, so once I can make it pass Simh, then I can use it on the real Hardware..
I fixed T3, now to T4..
I fixed T4, now to T5..
I fixed T5.. I passes down through T20..
T20A has a problem..
Here is the Code for T20 and T20A.. I have Not inserted the comments in my code listing, BUT, I will insert what there is here for Your Enjoyment..

543 ;TEST UPPER REGISTER SET (R13) IN AUTO-INCREMENT MODE
544 002714 005037 001004 T20: CLR TEMP+2 ; Pre Set Memory Address
545 002720 012737 177777 001002 MOV #-1,TEMP
546 002726 012737 004000 177776 MOV #BIT11,PSW ;Switch to upper Register set
547 002734 012703 001002 MOV #TEMP,R13 ;Load Register
548 002740 012337 001004 MOV (R13)+,TEMP+2 ; Move Temp to Temp+2
549 002744 022737 177777 001004 CMP #-1,TEMP+2 ; Was Temp moved
550 002752 001401 BEQ .+4
551 002754 000000 HLT ; ERROR
552 002756 022703 001004 CMP #TEMP+2,R13 ;Did R13 Increment
553 002762 001401 BEQ .+4
554 002764 000000 HLT ; Error!! R13 did Not Auto-Increment
555 002766 010701 SCOPE
556
557 ;TEST UPPER REGISTER SET (R14) IN AUTO-DECREMENT MODE
558
559 002770 012737 001002 001004 T20A: MOV #TEMP,TEMP+2
560 002776 005037 001002 CLR TEMP
561 003002 012737 004000 177776 MOV #BIT11,PSW
562 003010 013704 001006 MOV TEMP+4,R14
563 003014 014437 001002 MOV -(R14),TEMP
564 003020 022737 001002 001002 CMP #TEMP,TEMP
565 003026 001401 BEQ .+4
566 003030 000000 HLT
567 003032 022704 001004 CMP #TEMP+2,R14 ; Did Register Auto-Decrement
568 003036 001401 BEQ .+4
569 003040 000000 HLT
570
571 ;TESTS 21 AND 22 HAVE BEEN DELETED

It fails at line 567 '003032 CMP #TEMP+2,R14..

I am going to try changing line 567 '003032 CMP #TEMP+2,R14 to 567 '003032 CMP #TEMP+4,R14, and see if that helps
OR change line 562 '003010 MOV TEMP+4,R14, to 562 '003010 MOV TEMP+2,R14, and see if that makes any difference in Simh..

I found the Mistake 562 '003010 MOV TEMP+4,R14, should have been 562 '003010 MOV #TEMP+4,R14..

THANK YOU Marty
 
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Hi All;

T25 failing at 3304..

611 ;TEST THAT JSR INST OPERATES PROPERLY WITH REG SET BIT SET
612
613 003232 012706 000500 T25: MOV #KPTR,KSP
614 003236 012700 000001 MOV #BIT0,R0
615 003242 012737 004000 177776 MOV #BIT11,PSW
616 003250 012700 000400 MOV #BIT8,R10
617 003254 004037 003262 JSR R10,T25B
618 003260 000000 T25A: HLT
619 003262 022706 000476 T25B: CMP #KPTR-2,KSP
620 003266 001401 BEQ .+4
621 003270 000000 HLT
622 003272 022737 000400 000502 CMP #BIT8,KPTR+2
623 003300 001401 BEQ .+4
624 003302 000000 HLT
625 003304 022700 003260 CMP #T25A,R10 ; Is Return Address in R10
626 003310 001401 BEQ .+4
627 003312 000000 HLT ;Error !! Return Address Not saved in R10
628 003314 005037 177776 CLR PSW
629 003320 022700 000001 CMP #BIT0,R0
630 003324 001401 BEQ .+4
631 003326 000000 HLT
632 003330 010701 SCOPE
633
634

Here are the comments..

T25: MOV #KPTR,KSP ;Initialize Stack Pointer
MOV #BIT0,R0 ;Pre Set R0
MOV #BIT11,PSW ;Set Register Set Bit
MOV #BIT8,R10 ;Preset R10
JSR R10,T25B ;Go to T25B and Save R10 on Stack
T25A: HLT ;JSR did not go
T25B: CMP #KPTR-2,KSP ;Stack Pointer did Not Decrement
BEQ .+4
HLT
CMP #BIT8,KPTR+2 ;Was old Contents of R10 Saved ??
BEQ .+4
HLT ;Error !! R10 Not saved
CMP #T25A,R10 ;Is Return Address in R10
BEQ .+4
HLT ;Error !! Return Address Not saved in R10
CLR PSW
CMP #BIT0,R0 :R0 left Unchanged
BEQ .+4
HLT ;R0 got changed
SCOPE


Here is the Link to the Page with the original program listing --

http://bitsavers.trailing-edge.com/pdf/dec/pdp11/xxdp/diag_listings/1140_45/

And here is the name of the PDF --

006_DCKBH-A_1145_REGS.pdf

THANK YOU Marty
 
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Code: 
613 003232 012706 000500           T25:  MOV #KPTR,KSP
614 003236 012700 000001                 MOV #BIT0,R0
615 003242 012737 004000 177776          MOV #BIT11,PSW
616 003250 012700 000400                 MOV #BIT8,R10
617 003254 004037 003262                 JSR R10,T25B
618 003260 000000                  T25A: HLT
619 003262 022706 000476           T25B: CMP #KPTR-2,KSP
620 003266 001401                        BEQ .+4
621 003270 000000                        HLT
622 003272 022737 000400 000502          [B]CMP #BIT8,KPTR+2[/B]
623 003300 001401                        BEQ .+4
624 003302 000000                        HLT
625 003304 022700 003260                 CMP #T25A,R10   ; Is Return Address in R10
626 003310 001401                        BEQ .+4
627 003312 000000                        HLT             ; Error !! Return Address Not saved in R10
628 003314 005037 177776                 CLR PSW
629 003320 022700 000001                 CMP #BIT0,R0
630 003324 001401                        BEQ .+4
631 003326 000000                        HLT

Line 622 should be cmp #bit8,kptr-2 not kptr+2; it is referencing the wrong location on the stack (which grows down on the PDP11).

Don
 
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Hi All;

THANK YOU !!, Don for coming through Again..

I knew that there had to be SomeOne who Understood these kind of things, Could see the Problem right away..
And Tell me what needed to be done..

I have made the Correction in the Primary file, and will try and Run it in a minute, and Let You know the Result..

Here is the Next problem -- (I have included the Comments)

719 ;CHECK THAT ALL BITS IN THE MICRO BREAK REG CAN BE SET/CLEARED
720
721 003642 012700 000001 T33: MOV #1,R0
722 003646 012702 177770 MOV #UBREAK,R2 ;Get address of MicroBreak Register
723 003652 010012 T33A: MOV R0,(R2) ;Load bit into Register
724 003654 011203 MOV (R2),R3 ;Get result
725 003656 020003 CMP R0,R3 ;Compare result and Test bit
726 003660 001401 BEQ .+4
727 003662 000000 HLT ;Error !! Test Bit R0 did not set Micro Register
728 003664 040012 BIC R0,(R2) ;Clear Test Bit in Register
729 003666 011203 MOV (R2),R3 ;Get result
730 003670 001401 BEQ .+4
731 003672 000000 HLT ;Error !! Test Bit did not get cleared
732 003674 106300 ASLB R0 ;Shift Test bit until Done
733 003676 103365 BCC T33A
734 003700 010701 SCOPE
735
736 ;CHECK THAT RESET DOES NOT CLEAR MICRO BREAK REGISTER
737
738 003702 012737 177777 177770 T34: MOV #-1,@#UBREAK ;Set all 1's into register
739 003710 122737 177777 177770 CMPB #-1,@#UBREAK ;check result
740 003716 001401 BEQ .+4
741 003720 000000 HLT ;Error !!!
742 003722 000005 RESET ;Reset does not clear register
743 003724 122737 177777 177770 CMPB #-1,@#UBREAK ;Check that Reset did not clear any bits
744 003732 001401 BEQ .+4
745 003734 000000 HLT ;Error !!
746 003736 010701 SCOPE
747

From Here it goes to PC = 000010 ..

I wonder if the problem is with the CMPB, in that it should be CMP instead.. No, I see why it's CMPB from earlier code, so that not the reason.. But, it still could be the CMPB Instruction..
But of course it could be ,@#UBREAK or the #-1 ..

I can start the program from Simh to start at the Second CMPB #-1,@#UBREAK ;Check that Reset did not clear any bits.. And it Traps at the Second HLT line..
Which would seem to Indicate that the Test is Failing.. Along with the first test of the CMPB as well..

I fixed one other Problem, where I had an '=' instead of an '+', in the code that starting @200 jumps to and so the code would hang..
So the above is the Only thing keeping the program from Looping over and over for 1000 loops, to pass the Test..

THANK YOU Marty
 
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It appears from looking at the PDP11 SIMH sources that the UBREAK (MicroBreak) register is only partially implemented for the 11/45 model. It is implemented as READ ONLY, so any writes to it will timeout (trapping thru location 4).

Code: 
/* CPU control registers - 11/45 */

t_stat CPU45_rd (int32 *data, int32 pa, int32 access)
{
switch ((pa >> 1) & 017) {                              /* decode pa<4:1> */

[B]    case 014:                                           /* MBRK */
        *data = MBRK;
        return SCPE_OK;
[/B]
    case 015:                                           /* PIRQ */
        *data = PIRQ;
        return SCPE_OK;

    case 016:                                           /* STKLIM */
        *data = STKLIM & STKLIM_RW;
        return SCPE_OK;
        }                                               /* end switch PA */

*data = 0;
return SCPE_NXM;                                        /* unimplemented */
}

t_stat CPU45_wr (int32 data, int32 pa, int32 access)
{
switch ((pa >> 1) & 017) {                              /* decode pa<4:1> */

    case 015:                                           /* PIRQ */
        ODD_WO (data);
        put_PIRQ (data);
        return SCPE_OK;

    case 016:                                           /* STKLIM */
        ODD_WO (data);
        STKLIM = data & STKLIM_RW;
        return SCPE_OK;
        }                                               /* end switch pa */

return SCPE_NXM;                                        /* unimplemented */
}


This is an oversight/bug in SIMH (as the register really exists in 11/45 hardware as a r/w register), but no system software would probably ever use this register. Usually only used by techs in the lab troubleshooting with a scope.

It is fully implemented for the 11/70 SIMH cpu type, however, so if you:

set cpu 11/70

before running that diagnostic I bet that test will pass.

Don
 
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Hi All;

Don, Thank You for Your Research, and Response..

"" It is fully implemented for the 11/70 SIMH cpu type, however, so if you:

set cpu 11/70

before running that diagnostic I bet that test will pass. ""

I will Try this right away and Tell You what happens..

No, it makes No difference.. I have even for the sake of making things work along Committed out T33 and T34, and it still will not fully Pass..
Here it is with the set CPU to 11/45, but set CPU to 11/70, does the same thing..

PDP-11 simulator V4.0-0 Beta git commit id: 6210ba20
sim> set cpu 11/45
Disabling XQ
sim> set 256K
sim> load reg-11-45.bin
sim> go 200

HALT instruction, PC: 000014 (000016)
sim> go 3642

HALT instruction, PC: 000014 (000016)
sim>

The go at 200 is the normal starting address, and the go at 3642 is after it has made one pass, it takes a minute to run through, but it ends up at the same place.. PC = '000014..
I will try it tomorrow on the Real thing and see if that makes any difference or not..

THANK YOU Marty
 
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Here is a SIMH test (I sadly don't have either a real 11/45 or 11/70 ...):

Code: 
PDP-11 simulator V4.0-0 Beta        git commit id: 59947e8c
sim> de 0 0
sim> go 0
HALT instruction, PC: 000002 (HALT)
sim>
sim>
sim> set cpu 11/70 64k
Disabling XQ
sim> ex mbrk
MBRK:   000000
sim> ex 17777770
17777770:       000000
sim> de 17777770 55
sim> ex 17777770
17777770:       000055
sim> ex mbrk
MBRK:   000055
sim>
sim>
sim>
sim> set cpu 11/45 64k
sim> ex mbrk
MBRK:   000000
sim> ex 17777770
17777770:       000000
sim> de 17777770 55
Address space exceeded
sim> ex 17777770
17777770:       000000
sim> de mbrk 55
sim> ex mbrk
MBRK:   000055
sim> ex 17777770
17777770:       000055
sim>
sim>

So something interesting going on. Exam/deposit of uBRK works on 11/70 referring to both the CPU register 'MBRK' and the physical address 17777770.

On the 11/45, exam/deposit of the uBRK register works using the CPU register 'MBRK', but only exam (reads) work for the physical addrress 17777770. Deposit (writes) time out.

This is consistent with the 11/45 CPU register access code I detailed earlier, and in any event it is a bug in the SIMH simulation of the 11/45 CPU.

Don

PS: I wrote a little macro11 test program that reads / writes both bytes and words to address 177770 (the uBRK cpu register). As expected, it passes SIMH on the 11/70 cpu type, but on the 11/45 cpu type it traps thru 4 (timeout vector) on writes (byte or word) to 177770. Reads (byte and word) to 177770 both work.

PS2: Looking at the SIMH PDP-11 code further, the 'MBRK' cpu register exists as a pseudo-register on *ALL* PDP-11 models, whether it exists in the physical hardware or not. So one can even access the MBRK register on an 11/04 where it clearly does not physically exist. References to the physical hardware address 17777770 are PDP-11 model specific, however, and as noted above the modeling of this register is broken on the 11/45 cpu type.
 
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Hi All;

Thank You, Don for Your update on what is happening on the Simh program..

I am wondering if the code for UBREAK for the 11/70 could be copied to the 11/45 section of the code, just for completeness..

I will be gone today, so I do not have time to dig very deep into why it is trapping at PC= '000014.. And where in the program that this is happening.. Nor to run it on the real machine..

Since I commented out Tests T33 and T34, I thought that it should then be able to Pass all of the Rest of the program without trapping to any lower code locations.. I will look at T30 through T32..

I think I Found the Problem in the Code, This program (I think) was Originally made to Run under XXDP or something like it.. And so the Ending code reflected this.. I commented this out and Added a Halt Instruction, and Now it seems to be Running and NOT trapping at any of the lower addresses..

748 003642 005237 001000 END: INC ICNT
749 003646 023727 001000 001000 CMP ICNT,#1000
750 003654 001402 BEQ DONE
751 003656 000137 003704 JMP DONE1
752 003662 012737 000007 177566 DONE: MOV #7,TPBUF
753 003670 105737 177564 TSTB TPCSR
754 003674 100001 BPL .+4
755 ;MOV @#42,%2
756 ;BEQ DONE1
757 ;JSR 7,(2)
758 003676 000000 HALT ;NOP
759 003700 000240 NOP
760 003702 000240 NOP
761 003704 000137 001014 DONE1: JMP BEGIN
762

Simulation stopped, PC: 001632 (ASL @#1002)
sim> ex 1000
1000: 044751
sim> cont

If I change Address Location 3700 to '000000 it halts at PC = 3702 and Location 1000 contains 1000..
So NOW the Program is Working on Simh..
I will when I have Time Run the program on the PDP 11/45 without T33 and T34, and see if it passes, and if it does, then I will try and Run it with T33 and T34..

Thank You Don for All of Your Help !!!!

THANK YOU Marty
 
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Marty you are exactly correct ... this sequence is used at the end of pass code in diagnostics to detect, and return to, the XXDP monitor.

The green text is the 'standard' way for the diagnostic to return to the monitor. When originally loading the diagnostic XXDP will overwrite location 42 in low memory with the address it wants the diagnostic to return to when complete. In the diagnostic this location defaults to 0.

The brown text is typical for the diagnostic to run some number of passes (determined by the diagnostic writer) before checking whether to return to XXDP. Typically this loop count is set to run for a minimum wall clock time (like 10 seconds, depends on the nature of the diagnostic).

Patching in NOP (000240) or HALT (000000) opcodes in various locations in this sequence will allow you to override this standard behavior.

Code: 
[B][COLOR="#880000"]748 003642 005237 001000          END:   INC  ICNT
749 003646 023727 001000 001000          CMP  ICNT,#1000
750 003654 001402                        BEQ  DONE
751 003656 000137 003704                 JMP  DONE1[/COLOR]
[/B]752 003662 012737 000007 177566   DONE:  MOV  #7,TPBUF
753 003670 105737 177564                 TSTB TPCSR
754 003674 100001                        BPL  .+4
[B][COLOR="#008800"]755 003676 013702 000042                 MOV  @#42,R2
756 003702 001404                        BEQ  DONE1
757 003704 004712                        JSR  PC,(R2)
758 003706 000240                        NOP
759 003710 000240                        NOP
760 003712 000240                        NOP[/COLOR]
[/B]761 003714 000137 001014          DONE1: JMP BEGIN
 
Hi All;

Don, thank You for the Explanation..

I have Loaded and Run the Program on the Real PDP 11/45, and it Passed..
Now I need to Add back in Tests T33 and T34, Re-assemble it and then Run it again..

And, Yes it Runs and Passes with Tests T33 and T34 Included, on the Real PDP 11/45..

I just got a USB to Serial unit, and I have Tested it on my USB only computer, and it worked fine..

So, I will set up the 11/45 with two Serial Ports, and try to Load and Run TU58 Emulator(s)..

THANK YOU Marty
 
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Marty said:
Hi All;
And, Yes it Runs and Passes with Tests T33 and T34 Included, on the Real PDP 11/45..
THANK YOU Marty
Click to expand...

SimH is not very good at running diagnostics. The simple GKAAA0 11/04 CPU test works, but not the GKAABC0 interrupt test. I had similar problems with the VAX-11/750. Instruction tests work but not for example the Cache/TB test.

Tested a 11/34 MMU test (FKTHB0). Didn't pass on SimH either. So SimH is not a god reference when it comes to running diagnostics and if I understand Bob Supnik correctly this is not the goal of SimH.
 
MattisLind said:
SimH is not very good at running diagnostics. The simple GKAAA0 11/04 CPU test works, but not the GKAABC0 interrupt test. I had similar problems with the VAX-11/750. Instruction tests work but not for example the Cache/TB test.

Tested a 11/34 MMU test (FKTHB0). Didn't pass on SimH either. So SimH is not a god reference when it comes to running diagnostics and if I understand Bob Supnik correctly this is not the goal of SimH.
Click to expand...

100% correct. Many diagnostics make use of hardware dependent behavior or specific 'maintenance modes' that are not used by any standard operating system software, and are only used by very specific hardware focussed diagnostics.

That being said, SIMH 11/70 implements the MBRK (microbreak) hardware register access correctly, but SIMH 11/45 does not (implements reads only, writes time out). Probably would never be noticed in any standard DEC operating system, but in fact what SIMH implements for the 11/45 is not functionally correct.

Most/all of the other tests that Marty was running however were pretty vanilla flavored PDP-11 code which would have to run correctly on SIMH.

Don
 
Hi All;

Thank You, MattisLind and Don, for Your feedback..

"" Most/all of the other tests that Marty was running however were pretty vanilla flavored PDP-11 code which would have to run correctly on SIMH. ""

Which is Exactly what I would want it to do..
In other Words, to shake out any Spelling (code) mistakes, before I try and Run it on the Real thing..
When there is a Problem, to ask for Help from People who Understand Programming and Code, before trying to Run on the Real Hardware..

My Goal is to Build and Assemble all of the Tests for the PDP 11/45, that are in Listing form only, and build Binary files for these, so they can be used, by Everyone, not only me..

I have One of them done, I have three more short ones to do Next on the List, while, I get the Hang of doing this,
SPL, STACK LIMIT and STATES, before going to the Large programs like INSTRUCTION EXERCISER..


THANK YOU Marty
 
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I just for fun ran through CKBAB0, CKBBB0, CKBCC0, CKBDC0 and CKBIB0 successfully in SimH. CKBEC0 gave me a halt at 1464.

I didn't find the one you are running on the XXDP image I have here.
 
Hi All;

MattisLind, Thank You for your information..

"" I didn't find the one you are running on the XXDP image I have here. ""

That is 'Why' I am typing these programs in and Assembling them..
So, that the Binary files will be available for others to use..
I haven't Looked at what is in the XXDP files, I probably should, all I am trying to do is to be able to totally check out my 11/45..
Maybe, that is too much to ask..

I have Assembled Diane's Tu58 BootLoader, I still need to Transfer it to the Other Computer.. Done
And, I need to Remember/Familiarize myself With the TU58 Booting process..
I will need to Go to Don's TU58 page and have a look.. done
Before Asking any Questions..

I am where I was before, things not working.. But, before I ask for Help, I will look at thing more carefully..
I need the make sure that the file for XXDP is the correct one for a TU58..
It wasn't.. What I had was WAAAAY too Big..
Alot, better this time through..
Now I am seeing NULLS, and I know Exactly where to Look to see even though I have two switch positions SET, they may Not be Right, and without this Set, NULLS would be all I would get..
I will Check, it out..
One fo the switch contacts was Not conducting, some Deoxit worked wonders..
It's Better, but Not Right..

C:\pdp-11>tu58ew -p 4 -s 9600 -r tu58xxdp.dsk
info: unit 0 r file 'tu58xxdp.dsk'
info: serial port 4 at 9600 baud
info: TU58 emulation start
info: R restart, S toggle send init, V toggle verbose, D toggle debug, Q quit
info: emulator started
info: verbosity set to ON; debug ON
info: devrxavail(): status=0x0000 avail=4
info: flag=0x04 last=0x00
info: <INIT> seen
info: flag=0x04 last=0x04
info: <INIT> seen
info: <INIT><INIT> seen, sending <CONT>
info: flag=0x08 last=0xFF
info: <BOOT> seen
info: boot unit=0 blk=0x0000 cnt=0x0200

AnyOne, see something ?? Thank You..

I Looked at some of the PDP 11/45's memory and the Listing for address '0000 - 640, and it appears to be there..
But, I don't know what address to try and execute from..

Tomorrow, I will Double check all of the Switch settings on the TU58 I/O Serial Board, along with a meter on the Switches as well.. Maybe another Switch isn't making contact..

M-Thompson, I haven't forgotten About what You Suggested, I have never used it and I don't need to add to my Confusion.. I have enough already, Hopefully, somewhere down the Line.. I can figure out whether, I can make sense of it and use it..

THANK YOU Marty
 
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Diane's code is doing a CLR PC as the last instruction. I.e the code loaded shall be started at 0. But that should happen automatically if you entered and ran the full bootstrap.

The TU58 dump look fine to me as far as I remember. You might increase verbosity by pressing V.
 
Hi All;

Thank You, MattisLind, for the confirmation..

I For the Fun of it did start it at '0000 and it did 14 Reads, before stopping again.. But, I didn't know what to do next..

"" The TU58 dump look fine to me as far as I remember. You might increase verbosity by pressing V. "

I had Both D and V turned on, when I did the 14 reads, I just didn't put any of it here, as it would be way tooo Long for posting..

Here is the end of what it Sent..


info: flag=0x00 last=0x02
info: <NULL> seen
info: flag=0x04 last=0x00
info: <INIT> seen
info: flag=0x04 last=0x04
info: <INIT> seen
info: <INIT><INIT> seen, sending <CONT>
info: flag=0x02 last=0xFF
info: getpacket()
02 0A
02 00 00 00 00 00 00 02 0E 00
12 0C
info: opcode=0x02 length=0x0A
info: read unit=0 sw=0x00 mod=0x00 blk=0x000E cnt=0x0200
info: putpacket()
01 80
B7 11 1E 03 37 0A F8 04 C0 11 C0 65 0C 00 12 88 00 88 07 01 3D 01 C0 0B 04 03 C0 61 C0 E5 1C 0C
24 88 C6 1D FC 02 87 00 54 1A D2 1A DA 1A F0 18 24 19 B4 19 0C 1B C8 19 DE 19 30 1A 42 1A A6 1A
8C 1A 22 18 BA 1A CA 1A 68 1A 00 00 53 4D 00 53 4D 49 00 43 4D 49 00 4C 00 53 00 52 00 45 0 43
00 47 4F 54 4F 00 57 41 49 54 00 51 55 49 45 54 00 50 52 49 4E 54 00 45 4E 44 00 51 55 49 54 00
49 16
info: putpacket()
01 80
49 46 4C 4D 44 00 49 46 45 52 52 00 49 46 00 00 01 88 A0 00 C8 8B 28 03 17 A2 3B 00 25 03 57 A0
3A 00 22 03 C4 15 7E FF C4 61 C2 15 9C FF C2 61 03 10 73 A0 FF FF 02 03 D2 A4 FB 03 F2 8B FF FF
07 02 F3 8B FF FF 0C 03 D7 AC FF FF 20 00 08 03 D2 8B FE 02 D4 0B EC 02 C0 15 EA 0C 02 88 04 01
04 13 C4 6DEA 03 CC 09 8F 01 3F 45 52 0D 0A 00 B7 8A 10 04 01 88 15 01 26 10 01 A4 FE 02 F0 95
08 FC
info: putpacket()
01 80
2E 00 FF FF D0 95 42 00 D0 95 49 00 D0 95 43 00 08 8A 80 15 F7 65 04 00 D0 03 01 0A 0C 88 37 8A
E2 03 87 00 F7 09 02 00 15 01 F7 15 01 00 CC 03 F7 15 01 00 9C 03 57 20 2F 00 04 02 1E 88 09 01
37 10 8E 03 09 88 05 01 C0 35 01 00 02 02 37 10 AA 03 87 00 F7 25 01 00 A2 03 0 03 F7 1D 9C 03
9C 03 07 01 F7 25 01 00 94 03 03 02 F7 15 80 00 8C 03 19 88 01 9C 02 00 C1 E5 30 00 5F 90 20 00
7D 72
info: putpacket()
01 80
1F 9C 03 00 21 00 DF 1D 6E 03 18 00 DF 1D 6A 03 1A 00 E6 11 CE 65 4E 01 9F 15 22 00 B7 11 84 01
FF 09 5A 03 C6 1D 7C 01 F7 09 52 01 F7 09 36 02 00 0A 87 00 01 88 87 00 26 10 F7 09 6C FF B7 15
28 03 F7 09 2E FF C6 01 01 88 08 01 20 88 E6 1D 50 01 F7 09 2A FE B7 15 48 01 88 87 00 C2 15
50 1C C2 6D EA 02 84 10 01 88 21 01 14 94 01 A2 FD 02 0C 8A F7 8A 19 03 00 88 01 01 04 01 37 0A
7E 0F
info: putpacket()
02 0A
40 00 00 00 00 00 00 02 00 00
42 0C
info: read time=640ms
info: flag=0x00 last=0x02
info: <NULL> seen
info: flag=0x04 last=0x00
info: <INIT> seen
info: flag=0x04 last=0x04
info: <INIT> seen
info: <INIT><INIT> seen, sending <CONT>
info: flag=0x02 last=0xFF
info: getpacket()
02 0A
02 00 00 00 00 00 00 04 14 00
18 0E
info: opcode=0x02 length=0x0A
info: read unit=0 sw=0x00 mod=0x00 blk=0x0014 cnt=0x0400
info: putpacket()
01 80
C0 0B 02 03 02 88 07 88 C6 15 C4 1C C6 6D C0 04 C5 1D B6 04 F7 09 CE 03 E6 15 E0 00 E6 11 CE 65
06 00 02 00 C0 11 C0 65 DA FF 12 88 F7 8B DF 04 02 03 77 00 D6 00 F7 09 22 03 1C 88 07 88 C0 95
2E 00 04 88 00 0A 16 88 00 88 A0 00 F7 09 02 00 DB 01 01 88 A0 00 C8 8B 26 03 C4 15 98 00 C4 61
C2 15 7B00 C2 61 03 10 73 A0 FF FF 02 03 D2 A4 FB 03 F2 8B FF FF 0B 02 F3 8B FF FF 10 03 D7 AC
BF 26
info: putpacket()
01 80
FF FF 20 00 0C 03 D7 AC FF FF 2F 00 08 03 D2 8B FE 02 D4 0B E8 02 C0 15 B0 18 02 88 04 01 04 13
C4 6D 2C 04 CC 09 87 00 C0 15 C2 18 02 88 87 00 3F 20 49 4E 56 41 4C 49 44 20 43 4F 4D 4D 41 4E
44 00 3F 20 49 4E 56 41 4C 49 44 20 46 49 4C 45 4E 41 4D 45 00 3F 20 42 41 44 20 41 44 44 52 00
FF 44 41 54 45 00 56 54 00 4C 00 53 00 52 0043 00 44 00 45 00 48 00 00 B6 1A B0 1A 36 19 6E 19
B5 A7
info: putpacket()
01 80
EC 19 30 1A 12 1A 9A 1A B8 1A 00 00 B7 8A 5C 06 C2 11 C2 65 41 F2 C0 1D CC 03 90 94 FE 02 C0 1D
C4 03 01 0A 20 88 F7 09 22 01 C1 9D E3 03 C2 9D DE 03 5F 00 40 02 B7 8A CA 03 01 88 16 01 26 10
01 A4 FE 02 F0 95 2E 00 FF FF D0 95 42 00 D0 95 49 00 D0 95 3F 00 08 8A 80 15 F7 65 04 00 8A 03
01 0A 0C 88 37 8A 9C 03 87 00 77 00 3A FF F7 09 04 0012 87 12 01 F7 15 01 00 80 03 09 88 0B 01
07 41
info: putpacket()
01 80
C0 35 01 00 03 02 37 10 72 03 05 01 C0 15 D5 18 02 88 B1 00 01 01 A1 00 87 00 F7 25 01 00 5C 03
04 03 F7 1D 56 03 56 03 07 01 F7 25 01 00 4E 03 03 02 F7 15 80 00 46 03 19 88 01 9C 02 00 C1 E5
30 00 5F 90 20 00 DF 9D 3D 03 21 00 DF 1D 28 03 18 00 DF 1D 24 03 1A 00 1F 0A 22 00 DF 15 01 00
2A 00 FF 09 18 03 F709 FC 01 87 00 01 88 0F 01 26 10 F7 09 80 FF B7 15 F0 02 08 87 B7 8A 05 03
ED A4
info: putpacket()
01 80
F7 09 36 FF 37 8A FD 02 F7 09 8E FF 87 00 77 00 96 FE C0 11 C0 65 10 00 01 0A 0C 88 F7 15 01 00
DA 02 BB 01 44 49 52 2E 53 59 53 00 51 56 00 00 01 88 1F 01 20 88 D0 95 2E 00 C2 15 03 00 D0 95
43 00 C2 0A FC 02 08 8A F7 09 2A 00 C2 15 06 00 C3 1D 70 02 C3 E5 00 04 E6 10 F7 09 26 01 83 15
DF 45 0100 2A 00 C2 1D 5E 02 C1 15 26 03 77 00 88 01 77 00 32 FE C2 15 18 1C C2 6D 52 02 01 88
28 5B
info: putpacket()
01 80
01 01 C0 0A 12 94 FE 02 C0 15 9E FF C0 61 F7 09 28 01 02 87 B7 0A FC 04 87 00 09 88 08 01 35 90
FE FF C0 45 F8 FF C0 65 30 00 37 90 28 02 87 00 77 8A 5A 02 87 00 25 88 01 88 04 01 17 A2 4C 00
01 02 1B 88 C0 11 C0 65 20 00 0A 88 11 88 F5 1D 98 02 06 00 C0 15 6C 1D C0 6D F4 01 03 88 F7 0B
88 02 F4 02 8700 48 45 4C 50 2E 54 58 54 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
71 82
info: putpacket()
01 80
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 26 11 E6 10 A6 10 F7 09 0C FC 82 15 83 15 84 15 02 00 7F 00 BA 01 F7 8B 56 04
03 03 C2 15 06 00 02 01 C2 15 0C 00 C3 1D 7801 16 01 F7 09 E6 FF 00 0A 13 88 F0 01 C0 1D 64 01
01 0A 01 64 37 20 60 01 FC 02 C1 2D 94 01 1B 03 C2 15 08 00 C3 1D 4C 01 C4 15 00 04 05 01 C4 15
27 C3
info: putpacket()
01 80
00 01 02 01 C4 15 00 02 C5 1D 3E 01 35 11 02 00 B5 10 06 00 F5 10 04 00 F5 15 03 00 08 00 FD 09
F6 FF 37 0A 5A 01 87 00 C2 15 10 00 C3 1D 18 01 F7 09 CA FF FF 09 10 01 87 00 C2 15 58 00 C2 61
CA 8B 0F 03 97 A4 2F 00 FB 02 0410 12 A5 FE 03 97 AC FF FF 2F 00 03 03 F2 8B FF FF F1 02 A1 00
01 01 B1 00 87 00 DF 15 26 1B 18 00 DF 6D E0 00 18 00 DF 15 E0 00 1A 00 87 00 D2 94 C1 0A FD 02
C0 64
info: putpacket()
02 0A
40 00 00 00 00 00 00 04 00 00
42 0E
info: read time=1263ms

It is Passing Information Back and Forth, Now whether it is Correct is another matter..
I can see the Led's changing when Information is being passed back and forth on my RS-232 Break-out Box..
After it is Done Sending I did try to start the real 11/45 at address '200 and at address '000000..
Something is happen, but NO screen action..
And on the Windows side it remains at where You see the last line info: read time=1263ms..

THANK YOU Marty
 
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Marty said:
C:\pdp-11>tu58ew -p 4 -s 9600 -r tu58xxdp.dsk
info: unit 0 r file 'tu58xxdp.dsk'
info: serial port 4 at 9600 baud
info: TU58 emulation start
info: R restart, S toggle send init, V toggle verbose, D toggle debug, Q quit
info: emulator started
info: verbosity set to ON; debug ON
info: devrxavail(): status=0x0000 avail=4
info: flag=0x04 last=0x00
info: <INIT> seen
info: flag=0x04 last=0x04
info: <INIT> seen
info: <INIT><INIT> seen, sending <CONT>
info: flag=0x08 last=0xFF
info: <BOOT> seen
info: boot unit=0 blk=0x0000 cnt=0x0200
Click to expand...

This is correct for the initial boot sequence when the toggle-in bootstrap (or the DD0 command is given to the M9312) is used and the emulator gets a 'read bootblock' command.

For reference, I uploaded a full XXDP boot sequence to my tu58em page: http://ak6dn.dyndns.org/PDP-11/TU58/tu58em/ so one could see all the blocks read (none are written) in sequence when booting an XXDP tape image. There are a total of 81 read commands issued to be able to get to the '.' prompt on the PDP-11/34 console.

Don
 
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