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PET ROM/RAM replacement board

bitfixer

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Hi there,

Created this thread to pick up the discussion of the collaborative PET ROM/RAM replacement board that a few people were talking about on another thread. Basically the goal is to create a small board which will replace the ROM and RAM in a given PET, and provide a simple way to try different ROM images, for PET repair, debugging, or just for fun. So hopefully this thread will provide a good platform to discuss how to proceed with the project.
 
So here are some current thoughts about how to approach the board design. These are just quick musings and feel free to jump in with different/better concepts:

The board will have pin headers on the bottom which fit into the 6502 socket, with appropriate spacing to avoid touching any mainboard components.
Components for the board:
socket for 6502 processor
ATmega8 (or similar) mcu, for pre-loading SRAM with a ROM image. The mcu will also control the reset line to the 6502.
128k SRAM (628128 or similar), of which the bottom half will be used.
address decoding/write protect logic. Writes/reads to RAM (0000-8000) will go through to the SRAM normally. Writes to the ROM portion will do nothing, reads from ROM will read normally from the SRAM at that address. Other masked addresses (I/O space, video RAM) will keep the SRAM deselected.
The logic can be in the form of a PAL/GAL or just discrete logic, depending on how complex it needs to be. I'm thinking to be hobbyist friendly it might be nice to use regular 74 series stuff, so no additional programmers are necessary.. but a programmable logic chip would save some space on the board probably.
uSD card for ROM image and other configuration storage. ROM images to load into SRAM can be held in files on the SD card filesystem. Other configuration settings (40 vs 80 column, etc) can be in another config file on the card.
And we'll need voltage protection for the SD card (zener diodes).

Any thoughts? How does this sound?
 
128k SRAM (628128 or similar), of which the bottom half will be used.

In theory I suppose one could try to emulate the paging logic used in the 8096-series series PETs to make use of the other half, but that gets badly into "feature creep" territory.


The logic can be in the form of a PAL/GAL or just discrete logic, depending on how complex it needs to be. I'm thinking to be hobbyist friendly it might be nice to use regular 74 series stuff, so no additional programmers are necessary.. but a programmable logic chip would save some space on the board probably.

Sticking with discrete logic would be nice as long as it doesn't make the board size too unwieldy. It's pretty cheap to get a programmer for an ATmega or the like, but so far as I know programming GALs or PALs is more of an investment. (Unless there are some inexpensive in-place programmable GALs that could be set up via, say, SPI, from the MCU?)

Any thoughts? How does this sound?

Here's sort of an off the wall idea:

How about a diagnostic option where one or two K of the SRAM is mapped over the VRAM space. Offer a header on the board for attaching a simple serial connection. (Perhaps it could be the same header/lines you'd use for programming the MCU, and you could use the same external dongle you'd use for that.) If the PET has a blown monitor, CRTC, or some other problem in the video section you could run the diagnostic program to test ROM/RAM/etc and the results would be written to the onboard RAM. Then... add some logic that could halt the 6502 and allow the MCU to read the contents of the VRAM block and stuff it out the serial port. (I'm not sure how the "halting" would work. Trigger an NMI and feed the 6502 NOPs?)
 
How about a simple ICE while you're at it? Remove the CPU completely, connect your PC via serial or USB and step through the memory map, writing and reading back RAM and reading the ROMs for comparison or checksums? I think the DRAM is refreshed independently of the CPU, no? I've always wanted to build a simple one using the PC parallel port...
 
Components for the board: socket for 6502 processor ATmega8 (or similar) mcu, for pre-loading SRAM with a ROM image. The mcu will also control the reset line to the 6502. 128k SRAM (628128 or similar), of which the bottom half will be used.

I'm OK with this although it seems like a bit of overkill compared to the simplicity of the Nickolas board.

I would like to also have a NOP Generator function for troubleshooting address circuitry shorts/opens in the PET (a common and difficult to find problem). It would only take an 8 bit tri-state register to hold the $EA op code, or perhaps the 'extra' 64K of SRAM could be filled with NOPs and enabled to allow the PET to increment through address space?

Some people will want this board to simply replace the PET memory and get their PET working, but others would like to use the board to troubleshoot the PET and get the mainboard back on the air.
 
I'm OK with this although it seems like a bit of overkill compared to the simplicity of the Nickolas board.

Well, I could be wrong (I often am), but just quickly reading the description of the Nickolas board it looks to me like it needs to have its GAL reprogrammed in order to behave differently? (The page talks of "personality chips.) That leads to:

Some people will want this board to simply replace the PET memory and get their PET working, but others would like to use the board to troubleshoot the PET and get the mainboard back on the air.

If one wants the same board to be able to work in both a "replace pieces" and a "diagnose problems" mode (without reprogramming a GAL or some other "hard rewiring") I sort of don't see how you could really get around having to make the board more complicated than the Nickolas board.

For instance, suppose you wanted the option of being able to replace/upgrade the lower 32k or RAM with onboard SRAM *or* allow write-through for diagnostic purposes. My assumption is that the GAL on the original board must at least suppress input on the data bus to the 6502 when mapping its own RAM there in order to prevent bus contention. (And potentially getting scrambled data from any chips left on the main board.) It seems you'll at the very least need a jumper to enable/disable RAM mapping. The same would go for ROM mapping, of course, if you want the option of accessing ROMs in the PET's sockets. And what about the possible usefulness of "hybrid" modes? A pretty good case could be made that the best/most universal solution would be to have a simple MMU that allows selective mapping of reasonably small pages. (2K would probably be enough. It appears at least that's about the granularity of the Nickolas board's GALs.)

If it could be *reasonably* done in discrete logic I could see great value in a board like that. The onboard MCU could read a configuration file stored on the flash card along with your firmware describing which 2k pages you wanted mapped to read/write SRAM, which would be preloaded with firmware and write protected, and which would be set to "transparent" and passed through to the PET hardware. This could allow all sorts of fun options:

* Map 2k of SRAM at the bottom of the memory map, allowing the zero page and stack to reside in known good RAM. This could allow an "advanced" diagnostic ROM suite to run and test the remaining motherboard RAM to locate bad bits or possible addressing issues.

* Override VRAM. (Optionally come up with some sort of way to read it out independent of the 6502.)

* Map a diagnostic ROM into the top 2 or 4k but leave the rest of the ROM area available for checksum testing. (It looks to me like the Nickolas board is all-or-nothing on ROM replacement unless you burned your own GAL.)

* Remap any other single ROM socket to SRAM to temporarily work around a bad BASIC ROM, or to map option ROMs or writable SRAM into the area under BASIC.

Of course, I have no idea how difficult it would be to construct a 2k-granular "MMU" out of discrete parts. Assuming we're limiting ourselves to a flat 64k memory map (no actual paging) that's 32 switches for "SRAM or BUS" and another 32 for SRAM write-protect.

As for the NOP generator I could see another possible use for the same data register you'd use to hold the NOP opcode. How about using the same register to optionally allow the MCU to feed the 6502 an arbitrary address to jump to following a RESET? Then you could map a diagnostic program somewhere other than F000 and leave the KERNEL ROM space mapped to the PET hardware.
 
Well, I could be wrong (I often am), but just quickly reading the description of the Nickolas board it looks to me like it needs to have its GAL reprogrammed in order to behave differently?
Eud,
The GAL and a DIP switch act as the Memory Mapper and currently provide for choosing between any of one of four 28K external blocks of EEROM/EPROM or the internal ROM. The RAM can be internal or mapped to external in blocks of 4K, 8K, 16K or 32K.

Right now the ROM equations in the GAL are ‘all or nothing’ between internal and external space, but it is capable of being mapped into 2K segments. However there is a severe limitation of seven product terms in the GAL/PAL for each output (although one could route an output back into the input array to expand terms, it could affect the Nickolas board).

But if the $9000-AFFF expansion ROM space is left internal only, then there would be room in the equations for a diagnostics block where the $F000 space is mapped external to hold test code and the rest is internal to allow that area to be tested. In this mode perhaps the first 4K RAM would be mapped external for scratch memory and the rest internal so it could be tested.

I do not have a Nickolas board so I have no real vested interest although I have the capability to program the GAL (actually PAL16V8 ) and supply it free (I have a pile) to users if we decide make kits.

But if you guys are willing to tackle a grand new design, I will support the project as best I can. I really think this type of board is needed as PETs are getting harder to maintain (especially the early types with the oddball ROM and RAM).
-Dave
 
My assumption is that the GAL on the original board must at least suppress input on the data bus to the 6502 when mapping its own RAM there in order to prevent bus contention. (And potentially getting scrambled data from any chips left on the main board.) It seems you'll at the very least need a jumper to enable/disable RAM mapping.

The Nick board uses the GAL to control the enable of a LS245 transceiver to isolate the data bus from the mainboard when external memory is mapped on. The direction of the transceiver is simply handled by the R/W signal. The new board will need this function also.

Two of the DIP switches are used to disable external ROM and RAM to allow the board to remain in place while the internal mainboard memory runs the machine with the 6502 on the external board.
 
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The Nick board uses the GAL to control the enable of a LS245 transceiver to isolate the data bus from the mainboard when external memory is mapped on. The direction of the transceiver is simply handled by the R/W signal. The new board will need this function also.

Spitballing, how about this as an idea for a "block MMU"? (Keeping in mind that I'm pretty much guessing whether any parts I name are appropriate based on quick reads of data sheets I found looking at Wikipedia's list of 74xx parts.)

An LS245 transceiver sits across the data bus at the CPU socket. A 74154 4-to-16 decoder is on the top 4 lines of the address bus, and the board also has two 8 bit addressable latches (74259?) and enough gates to combine the outputs from the latches with the outputs from the decoder into "chip selects". (This will give you a page size of 4k for the entire 64k address space of the 6502.) Then the "chip selects" are combined to provide two signals: an "Output Enable" for the LS245 and a select for the onboard RAM chip, which are mutually exclusive. If the socket bus is enabled output from onboard RAM is suppressed and vice-versa.

On powerup the onboard MCU preloads the appropriate places in the top half of the onboard RAM with your desired ROMs and programs the latches to say which pages map to the expansion board and which go to the mainboard with 4k granularity. Changing the memory map then just requires changing the contents of the latches.

Granted with a design like this we're pretty far over the parts count of the Anders board with the latches, decoder, and a pile of AND gates. But I'm sure someone more clever than me could find a way to streamline it some. :^/

(EDIT: I guess I forgot to include some registers for "write protect" in the ROM area. I suppose a simple way around it is to simply put a gate in to block writes to the entire upper 32k (perhaps minus the VRAM area?) and only allow the MCU write access to that. Alternatively you could add another latch and some AND gates to provide 8 RW/RO signals piggybacked off the top eight address-selector 74154 lines. I don't really see a reason why you'd need the ability to write protect pages in the bottom 32k.

And wait, I forgot another thing. We have a special case with the E800 area. That always has to write through. I suppose that could be solved by combining A11 with the E000 select from the 74154 and making that always write through regardless of the latch state.)
 
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And wait, I forgot another thing. We have a special case with the E800 area. That always has to write through. I suppose that could be solved by combining A11 with the E000 select from the 74154 and making that always write through regardless of the latch state.)

Yes, the I/O space is in an awkward place, but now you have covered the major requirements. Don't forget to handle the diagnostic mode and the NOP Generator. The diagnostic mode is simply a mapping of 4K external "ROM" with the test code at F000H and perhaps 2K (or 4K if it is easier) of external RAM mapped at $7800H. This will allow low RAM and especially zero page to be well tested. The test code could contain the normal PET initiation code (all relocated to the F000 area) and then branch to the diagnostic code rather than to the main start of BASIC.
-Dave
 
I guess in principle if you didn't care about having the memory map "soft-switchable" you could substitute a bank of 16 DIP switches for the two 8-bit latches in my vague design. It'd accomplish the same thing. I guess I'm just thinking if you *have* the MCU onboard anyway you might as well use it. (In principle if the MCU had enough I/O lines you could use them in place of the latches? But you'll probably need those I/O lines to communicate with the SRAM chip.)

Yes, the I/O space is in an awkward place, but now you have covered the major requirements. Don't forget to handle the diagnostic mode and the NOP Generator. The diagnostic mode is simply a mapping of 4K external "ROM" with the test code at F000H and perhaps 2K (or 4K if it is easier) of external RAM mapped at $7800H. This will allow low RAM and especially zero page to be well tested. The test code could contain the normal PET initiation code (all relocated to the F000 area) and then branch to the diagnostic code rather than to the main start of BASIC.

I wonder if these requirements would make it useful to allow a couple more manipulations to happen on the bus. I'm not sure mapping a page of memory "up high" really helps a whole lot for writing a diagnostic since it seems like you really have to have a working zero page and stack area to run complex code on the 6502. (in a non-spaghetti-ish way, anyway. Granted I'm barely qualified to comment on it.)

It would require putting some goo on the address bus, but what about having a register that would, say, swap the bottom 16k of address space with the next 16k? (Basically it would invert A14 if A15 were low.) With a setup like that you'd map "16-32k" to the board SRAM and "0-16k" to "write through" and set the invert register. Then you could run your full diagnostic using the board RAM as zero page and exercise the motherboard zero page by testing the block that appears at $4000. The control for the inverter could be an I/O pin on the MCU, again if you have it to spare.

For use as a NOP generator... set the entire 64k to SRAM, fill SRAM with NOPs, and include another override register for the I/O space "hole punch"?
 
I'm not sure mapping a page of memory "up high" really helps a whole lot for writing a diagnostic since it seems like you really have to have a working zero page and stack area to run complex code on the 6502.

One can just avoid using zero page addressing instructions, but I forgot that the stack space must be on page 1(severe restriction of the 6502 :( ). So you are right that diagnostic RAM had better be in low RAM.


It would require putting some goo on the address bus, but what about having a register that would, say, swap the bottom 16k of address space with the next 16k? (Basically it would invert A14 if A15 were low.) With a setup like that you'd map "16-32k" to the board SRAM and "0-16k" to "write through" and set the invert register. Then you could run your full diagnostic using the board RAM as zero page and exercise the motherboard zero page by testing the block that appears at $4000. The control for the inverter could be an I/O pin on the MCU, again if you have it to spare.
Pretty sneaky! That might work....

For use as a NOP generator... set the entire 64k to SRAM, fill SRAM with NOPs, and include another override register for the I/O space "hole punch"?

I'm not sure you would need an override since the mapping would point only to external memory. The NOP Generator would only be used in conjunction with a scope to check for problems in the address circuits. The address lines should be perfect square waves and the address decoder outputs will be 'easy to identify' pulses.
 
I'm not sure you would need an override since the mapping would point only to external memory. The NOP Generator would only be used in conjunction with a scope to check for problems in the address circuits. The address lines should be perfect square waves and the address decoder outputs will be 'easy to identify' pulses.

My feeling is you would need the override because the simplistic version I was thinking of was a simple hack around the fact that the page size of this design is 4k rather than 2k. (IE, it would use the absolute minimum number of gates to make $E800-$EFFF read/write-through regardless of what the read/write-through setting for what is otherwise the $E000-$EFFF block is.) If "NOP Mode" is done with the simple expedient of fetching NOPs from the onboard RAM if you didn't override the I/O punch-through then when the PC reached E800 the CPU would start fetching instructions from the mainboard's I/O area, not RAM, and thus would stall.

The other way to do NOP mode, of course, would be to have a device which hardcodes the NOP instruction on the data bus but can be switched on and off. Put a hardcoded NOP behind a 74LS244 buffer, perhaps?, and when then NOP switch is on chip select is disabled for both the 74LS245 bus transceiver *and* the SRAM and enabled for the NOP buffer. Then the only thing the CPU will ever see on the data bus is that hardcoded NOP.

Of course, that does have me thinking that you've going to have the MCU sitting on the data and address bus anyway. (For loading data into the SRAM in the first place.) Perhaps you could dispense with needing a "hard" NOP generator *or* filling SRAM with NOPs and simply have the MCU hold a NOP pattern on the data lines with the I/O pins it uses to communicate with SRAM when NOP mode is set? (You'd still suppress chip select on RAM and the bus transceiver, of course.)

(EDIT: Now... of course mentioning that the MCU is always on the bus anyway opens up the devious possibility of dispensing with the latch/decoder circuitry for memory mapping and having the MCU always-on monitoring the address bus and controlling chip select for SRAM and the bus transceiver. That'd cut the parts count *way* down, but... it would be very dependent on the MCU being fast enough to monitor the 6502's address bus in real time and make mapping decisions with perfect accuracy. If you could pull it off, though, you'd have the option of *completely arbitrary* page sizes.

And... this idea means we're probably looking at needing an MCU with around 30 I/O pins. That sounds bigger than what Gubbish had in mind originally.)
 
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Oh, while I'm blathering...

Another idea I had for a programmable memory mapper, which is silly, would be to use a fast RAM chip. How big it needs to be depends on the page size you want. A 64k chip would give you the ability to control the memory map in 1 byte increments, which is probably excessive. If you could find it a 256 *byte* one would be ideal, as that would give you perfect 8-bit page-size granularity. Anyway, the idea goes like this: (I'm going to pretend we're using a 256x8.)

Place the address pins of the memory chip on the CPU address bus starting at the *top*. The data lines are not connected to the CPU data bus. They're connected to the MCU (as is the address bus) so the chip can be loaded prior to 6502 reset, and they're *also* your chip select lines. Use the MCU to load a memory map into the chip. You have 8 choices for chip select, but for this instance we only really need 2 so let's say that D0 is connected to the bus transceiver and D1 goes to the board's SRAM. For any page you want mapped to the motherboard, write a 00000001 in the appropriate byte position. For anything that should go to the override SRAM, write 00000010. (If you don't want the other bits to go to waste you could always use them for things, like selecting write protect? You don't necessarily need to use an 8 bit wide chip, of course. A 4 bit one would do here. Or if in some other application you needed scads of selects you could use a 16 bit wide one?)

That's really pretty much it. I imagine there's timing concerns to worry about as the SRAM is probably not going to operate as fast as a plain TTL logic gate. (My thought is that if you were using a really fast RAM for this, 35ns, say, the delay between address input and data output should be good enough for the 6502's purposes, but there may well be things I'm not thinking of here. Perhaps you'd need a delay buffer in front of the "chip select" lines to make sure they don't actually actuate any devices until the output from the mapping SRAM is stable?)

I'm sure someone experienced with computer design can shoot this one down fast. The idea came to me because I vaguely remember some discussion somewhere about using a ROM chip as a replacement for a PAL. *If* it would work, though, it could take the parts count way down. (It would be combining the decoder chip and the memory latches in one package... and in essence that previous design can be thought of as the functional equivalent of a 16x1bit RAM.)
 
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I believe some early computer designs used ROMs as programmable logic. It would be a nice trick if it worked..
Just trying to make sure I understand the memory map used in the PET. As far as I gather,
0x0000 - 0x8000 maps to the max. 32k ram,
and above that there are regions for Video RAM, I/O, and ROM.
How do these regions differ between different PET models?
 
Thanks for the link Anders.
I'll study these and make some notes which include the address maps of the different models.
I like the idea of soft-switching as much as possible, to increase the flexibility of the design. I wonder if some extra pins on the microcontroller can be used as switches to control the different mapping options.

Also had another random thought on this which is probably an overly complicated feature, but wanted to see if this sounded interesting -
what if you could do some manipulation of the character ROM section of memory to do fully bitmapped graphics? You could use some or all of the unused 64k as a higher capacity VRAM, then rewrite sections of the character ROM section on the fly to draw pictures. Sounds complicated but potentially great for some PET demos.
 
I believe some early computer designs used ROMs as programmable logic. It would be a nice trick if it worked..

Yeah. It's an idea I had in a vacuum, but I think I'd have to puzzle over the data sheet for a given RAM for a while before even hazarding a guess about whether it would actually *work*.

The sad thing is *if* it would work a good part to use might be a fast 2114 or 2149. That would give you 4 "chip selects", which is probably enough, and if you chose to use all 10 address lines you'd get 64 byte page resolution. (And you'd be using a chip that a PET owner might already have lying around.)

Just trying to make sure I understand the memory map used in the PET. As far as I gather,
0x0000 - 0x8000 maps to the max. 32k ram,
and above that there are regions for Video RAM, I/O, and ROM.
How do these regions differ between different PET models?

I think you've pretty much got it, at least until you get to exotics like the Super Pet and the greater-than-32k models. (9000, 8096, etc.) And I *think* (I could be wrong) that for the most part those more exotic models use a mostly standard PET board with their extra features in the form of add-on daughter boards that can be pulled off for troubleshooting.

RAM counts from the bottom up (IE, from 0x0000 to the max of 0x7FFF), ROM counts from the top down, IE, later ROM versions with 18k of ROM instead of 14k map the additional chip in the 4k window underneath the lowest ROM in the original and 2.0 versions of BASIC. I/O is crammed into a 2k window at 0xE800, in which the 6522s and 6520s live. This means that the 14k or 18k of kernel+BASIC ROM actually maps to 16k or 20k of space, with the E000 ROM being only 2k in size. (Older PET motherboards only partially decode this space. Which means you need to use a ROM chip with the correct pinout in the 0xE000 slot or risk having ROM conflict with I/O.)

Expansion ROMs can live in the two or three 4k slots under BASIC, depending on which version, with the lowest ROM socket address being 0x9000. VRAM occupies the 0x800 space with either 1k (40 column) or 2k (8 column) of VRAM.

There's a 74154 4-to-16 address decoder on the PET mainboard, which is a good explanation as to why the memory map mostly oriented along 4k boundaries. That's actually the reason I suggested using that part in my first idea for a memory mapper. The weakness is, of course, is it needs some more stuff tacked onto it to handle the 2k I/O window. I'm sort of curious why Commodore didn't put the I/O at, say, 0x9000, or in the same 4k page as VRAM.
 
Also had another random thought on this which is probably an overly complicated feature, but wanted to see if this sounded interesting -
what if you could do some manipulation of the character ROM section of memory to do fully bitmapped graphics? You could use some or all of the unused 64k as a higher capacity VRAM, then rewrite sections of the character ROM section on the fly to draw pictures. Sounds complicated but potentially great for some PET demos.

The only weakness of the idea is that the character generator ROM isn't in the memory map. It's hardwired directly in front of the video output shift register. You could certainly replace it with a chunk of RAM and allow user-defined character sets but you'd have to have a jumper plug directly into the character ROM socket. :^/ (And program the RAM via a "back channel". The only manipulation the PET can do relating to the character set is it can set an I/O pin on... one of the 6520s or the 6522, I forget which, which sets the high address pin on or off and thus selects which of the two character sets is in use at any given time.)

(You'd also *probably* have to use a separate SRAM from the one you'd use for "main memory". Well, I guess you could use the same RAM if it were fast enough, but you'd have to handle bus contention issues since the output shift register is going to be operating asynchronously from the CPU's bus.)

I remember they used to sell programmable character generators for TRS-80s, like the "80-GRAFIX":

http://www.trs-80.org/80-grafix/

I guess I'd actually be sort of surprised if they didn't sell such a thing for PETs, so it might be a neat add-on. But it's probably a separate project from a memory replacement/troubleshooting board.

(Now what would be *really* neat is include the option for a DMA video generator on the board so you could map one or two K of VRAM over the video memory space and output to a composite RCA jack or something, for diagnosing PETs with bad video circuitry or dead monitors. But including video generation is... hard. I guess at that point we're only I/O chips away from having created a completely functional PET replacement motherboard.)
 
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what if you could do some manipulation of the character ROM section of memory to do fully bitmapped graphics?

Sadly, I've gotten this idea stuck in my head and I've been hashing out on a piece of paper how you might do it. An "80-Graphix" character generator that gives you 128 programmable graphics symbols would be pretty straightforward, although it would require both a board piggybacked into the character ROM socket with a 20-ish pin cable running to it from the internal expansion connector. But what I've been *really* been pondering beyond that is a way to give you the option of a full 320x200 bitmap. (For the purpose of brainstorming I'm ignoring the fact that 80 column PETs exist for the time being.)

Basically you get 10 useful address lines from the ROM socket. A3-A9 are generated by the data byte coming from VRAM, while A0-A2 are generated by the row counter. (A10 is the line that selects GRAPHICS or BUSINESS character sets and is controlled via an I/O port so it's not very useful. You'll notice we're missing 1 bit from the data byte as well. The top bit controls an inverter, making the top 128 characters appear as reverse-video copies of the bottom 128 that actually exist in the ROM.) For the 8000 bytes needed for 320x200 we'll need three more address lines. My thought is you could tap them from the top 3 address lines in one of the VRAM sockets. The simplest implementation then would essentially be the same as a "Character Generator" video system, but the screen would be broken into 8 zones which each used its own character set. (To treat it like a full-screen frame buffer you'd fill each block of 128 memory positions with the value 0 through 127 so the "data" provides the addressing. Confusing, eh?)

The thing I don't like about that is that ROM-centric addressing system is laid out so the 8 lines of 8 bits that make up a character are stored sequentially. This is fine for character graphics but it makes for a very non-linear framebuffer. (You'd have 1000 "cells" to deal with, which means when drawing lines you'll have to do some odd calculations when a line crosses between cells. It's certainly doable... I think that's how the TI 9918 video generator essentially worked when it was in "graphics mode", but it's weird.) Because of the way the addresses are generated I'm not sure there's a great way to fix that, and I guess it's not a huge deal.

The problem with this brute-force implementation of either the 128 character or the "full bitmap" version is that when it's switched on you'll lose normal characters unless you program them into the CHAR-RAM first. (And for every graphics character you'll lose a regular one.) For the 128 character version a thought I had was to put a probe on that "invert" line and use it as a chip select to chose whether a charact0er fetches from ROM or CHAR-RAM. You'd lose reverse-video characters (and all your graphics characters would be "backwards", but that's not a huge problem) but it makes it relatively easy to mix text and graphics. You could do the same thing with the "full-bitmap" version, for that matter, (in which case you'd fill only the parts of VRAM you want graphics on with the appropriate 128-255 value) but the other alternative I pondered would be to grab all 10 address lines from a VRAM socket and combine them with the 3 row addresses (A0-A2 from the charrom socket) and get your 13 address lines that way. In this scenario you'd ignore the values stored in the "main" VRAM... except for one thing. You could decide which *single character* you're willing to sacrifice (out of the 128), and put a 7 bit decoder on the board that works as the RAM/ROM select. (For instance, if you're willing to lose the "@" character just look to see if the data byte coming in on ROM socket A3-A9 is all zeros, and if it is enable CHAR-RAM to output to the shift register instead of the character ROM.)

Of course to write to the CHAR-RAM in either version you'll need 10-13 address lines, 8 data lines, chip select(s), and R/W signals. All of those are available on the internal expansion connector so you could run a shielded ribbon cable from that to the piggyback board in the character ROM socket. (Which also has pins in a VRAM socket, and potentially a clip or two to legs on other ICs.) Mapping the board at 0x9000 through 0xAFFF is the logical choice for the 8k version. (It would come with the bonus that when you're not using the board for graphics you could load extension ROM images into it.)

Unfortunately, when I think about this the chip count is intimidating, particularly for the full-fledged version. I imagine you'd need some MUX-es on the RAM address lines (like the 74157s in the original's video logic), and for 13 lines you'll need four. You might also want some '244 buffers on the data lines, maybe another buffer on the output side, a small handful of gates, plus a RAM chip and a socket for the character ROM. That's turning into a pretty big daughterboard.

Bleah. Probably best to forget it.
 
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