It doesn't matter Eudimorphodon.
I also don't have the motivation to really dive into this PAL U130.
Since before I already sorted out what should be done for the coprocessor to function.
It's not too complicated and it's described by IBM in the 5170 technical manual, seen in the Copam501 and written about in VLSI documentation of chipset ICs.
From all these sources I have drafted the schematic as seen in the KiCad screenshot, it can be found in the attachment.
Just for a try since it doesn't take much time, I have minimized U130 and programmed the results into a GAL.
During Landmark and Checkit tests using the GAL for U130 I can see the NPU performance so it seems to work at those tests, but I highly doubt that the equations are complete. It looks like some feedback got lost in the minimizations.
When I look at a gate representation I am seeing open ends.
And IBM did some weird stuff because they tied pin 11 to ground.
It seems they had some application but built in the option to disable certain logic by tying pin 11 to ground.
This generates 1 and 0 in the appropriate areas to disable the influence of pin 11.
Actually the NPU control is so simple that I will probably not be using these equations and spend days to write out equations and drawing gates, I will simply use the KiCad version in my attachment which reflects all the source information.
Those ICs you mentioned are bus transceivers and not involved in coprocessor latching of the ERROR condition.
/ERROR:
an error status input from the coprocessor
this reflects the ES bit of the coprocessor status word and indicates that an
unmasked error condition exists
The coprocessor asserts /BUSY_287 when it is executing a task.
This is passed through to the CPU on input /BUSY_286
Normally /BUSY_286 will follow /BUSY_287,
however if /ERROR is asserted while /BUSY_287 is active,
the /BUSY_286 output will be latched low and remains low,
until it is cleared by an IO write cycle to 0F0 or 0F1.
(0F0 = clear latched ERROR, 0F1 = reset the 287)
/IOW and 0F1 asserts a /RESET_287.
I can't really test the ERROR condition of the coprocessor because I don't know how to cause such a condition.
I don't know if those performance tests also check this function or not.
However all the descriptions are so clear I feel it can't miss. From the description in the IBM manual alone the circuit with a latch can be created and the Copam circuit diagram confirms this.
I will just implement the logic I created in mid december last year, and use a GAL to generate the decoding and control a normal latch IC as in the KiCad. So the gates will be replaced by programmable logic. I believe this is also what Copam did from their schematic. If there is any problem I can reprogram the GAL or whatever is used to test further.
I just post all these things here together in case someone is also searching for it.
Here is the result of the PAL read and minimization, however I don't believe it is fully functional to latch the ERROR condition of the NPU, so no guarantees, and I rather say it will probably fail at a real ERROR condition of the coprocessor, that's what I expect.
Rather, these equations at least allow the NPU to be able to pass some Landmark and Checkit testing without any crashes.
Code:
Name IBM-5170-U130 ;
PartNo 00 ;
Date 19-01-2023 ;
Revision 01 ;
Designer Rodney ;
Company - ;
Assembly None ;
Location None ;
Device G16V8A;
/* Dedicated input pins */
pin 1 = RESET; /* Input */
pin 2 = ERROR; /* Input */
pin 3 = 287_BUSY; /* Input */
pin 4 = XA0; /* Input */
pin 5 = XA3; /* Input */
pin 6 = XIOW; /* Input */
pin 7 = SM_IO; /* Input */
pin 8 = 287_CS; /* Input */
pin 9 = INTA; /* Input */
pin 11 = 11_NUSED; /* Input */
/* Programmable output pins */
pin 12 = NPCS; /* Combinatorial output */
pin 13 = 13_NUSED; /* Combinatorial output */
pin 14 = 14_NUSED; /* Combinatorial output */
pin 15 = 15_NUSED; /* Combinatorial output */
pin 16 = 16_NUSED; /* Combinatorial output */
pin 17 = RESET_287; /* Combinatorial output */
pin 18 = IRQ13; /* Combinatorial output */
pin 19 = 286_BUSY; /* Combinatorial output */
/* Output equations */
!286_BUSY =
!287_BUSY
# 11_NUSED;
!IRQ13 =
ERROR
# 287_BUSY;
!RESET_287 =
!RESET & !XA0
# !RESET & XA3
# !RESET & XIOW
# !RESET & SM_IO
# !RESET & 287_CS
# !RESET & !INTA;
!16_NUSED =
RESET
# !XA3 & !XIOW & !SM_IO & !287_CS & INTA;
!15_NUSED =
11_NUSED
# !RESET & !ERROR & !287_BUSY & XA3
# !RESET & !ERROR & !287_BUSY & XIOW
# !RESET & !ERROR & !287_BUSY & SM_IO
# !RESET & !ERROR & !287_BUSY & 287_CS
# !RESET & !ERROR & !287_BUSY & !INTA;
!14_NUSED =
ERROR
# 287_BUSY
# 11_NUSED
# !RESET & XA3
# !RESET & XIOW
# !RESET & SM_IO
# !RESET & 287_CS
# !RESET & !INTA;
!13_NUSED =
RESET & !11_NUSED
# ERROR & !11_NUSED
# 287_BUSY & !11_NUSED
# !XA3 & !XIOW & !SM_IO & !287_CS & INTA & !11_NUSED;
!NPCS =
XA3 & !SM_IO & !287_CS & INTA;
Unlike U87, U130 is not so essential to have a functioning AT, only important for the NPU to be fully functional.
In fact, U130 can be left out completely, which will only result in the NPU not being visible for programs which try to use it.
I will do some testing with the prototype to determine if the NPU functions.
I will do some research later about what could create those ERROR conditions so this can be fully tested.