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Serial PDP-8/e like computer?

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thunter0512

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I have been thinking about building a PDP-8/e clone using TTL logic and SRAM for memory but designing the CPU as a serial CPU like the PDP-8/s.

Rather than cloning the 8/s I thought it would make sense to make it functionally like an 8/e so that 8/e software would run unmodified.

This could be a small and cheap computer using a small number of SSI & MSI TTL ICs.

Any thoughts?
 
I was toying with the idea of doing something similar myself and was looking at basing it on the Fabri-Tek MP12.
Section 3 of the documentation has all the schematics...


The MP12 does use core memory and the front panel is a bit limited so it would need some tweaks but might make a good start.

Cheers,
Dave
 
I had a similar thought a good few years ago - but I have too much on at the moment...

You might find it useful to use a logic simulator (I use LOGISIM) to debug the design first though.

I have a basic '8' coded up in LOGISIM for the LD12 that you could start from if you like.

Dave
 
thunter0512 said:
I have been thinking about building a PDP-8/e clone using TTL logic and SRAM for memory but designing the CPU as a serial CPU like the PDP-8/s.

Rather than cloning the 8/s I thought it would make sense to make it functionally like an 8/e so that 8/e software would run unmodified.
Click to expand...

Interesting. Are you thinking of building this on an Omnibus card? Or as a stand-alone device? Or something else?
 
What do you envision for storage or I/O devices? Besides being able to execute the 8E instruction set, how much 8E hardware compatability are you thinking of? Would it be Omnibus compatible? Would it include EAE? A better/faster KK8A?
 
ftcnet said:
What do you envision for storage or I/O devices? Besides being able to execute the 8E instruction set, how much 8E hardware compatability are you thinking of? Would it be Omnibus compatible? Would it include EAE? A better/faster KK8A?
Click to expand...
I was thinking of a very basic PDP-8/s like machine with only the teletype interface. No Omnibus, EAE etc.
The only reason for the 8/e instruction set would be for better compatibility with software on paper taper - specifically diagnostics.
The 8/s was not quite compatible with any other PDP-8.
 
The differences between the Straight 8 and the 8/s in the OPeRate instruction were mostly because of the serial processing. Adding the ability to combine more of the patterns may add enough logic to make it overall less logic to do as a parallel processor. This is even before you add in the extra combinations found in the later machines.

I applaud any effort at producing such a machine and look forward to seeing what you discover along the way.
 
I recommend the following two books on digital design. They both feature building a PDP-8 computer from logic.

The Art of Digital Design - An Introduction to Top-Down Design - Franklin P. Prosser & David E. Winkel (ISBN 0-13-046780-4)
The PDP-8 Class Project or Resoling An Old Machine - Tom Almy (ISBN 9781790487974)
 
BitWiz said:
I recommend the following two books on digital design. They both feature building a PDP-8 computer from logic.

The Art of Digital Design - An Introduction to Top-Down Design - Franklin P. Prosser & David E. Winkel (ISBN 0-13-046780-4)
The PDP-8 Class Project or Resoling An Old Machine - Tom Almy (ISBN 9781790487974)
Click to expand...
I have both. :)
 
DougIngraham said:
The differences between the Straight 8 and the 8/s in the OPeRate instruction were mostly because of the serial processing. Adding the ability to combine more of the patterns may add enough logic to make it overall less logic to do as a parallel processor. This is even before you add in the extra combinations found in the later machines.

I applaud any effort at producing such a machine and look forward to seeing what you discover along the way.
Click to expand...
Thanks Doug.
Is there some document or website which describes the straight 8 versus 8/s differences and the reasoning for not including the missing OPeRate instructions?
I am surprised that the serial nature of the CPU is the reason.
 
> the reasoning for not including the missing OPeRate instructions?

I guess Doug gave it:

"Adding the ability to combine more of the patterns may add enough logic to make it overall less logic to do as a parallel processor."
Which I understand (non native English person here) as:
It did not make sense to add the OPeRate code because it would involve adding more integrated circuits than were saved by using a serial processor.
 
>>> It did not make sense to add the OPeRate code because it would involve adding more integrated circuits than were saved by using a serial processor.

Just to expand on the above statement a little bit.

The PDP-8/S is largely based on transistorised flip-chips as opposed to integrated circuits.

The OPeRate code was included (OPR groups 1 and 2) but compatibility with the 8/E was not quite the same (for example, the BSW bit combination is not supported). This means that any software that uses BSW (for the 8/E) will not work as intended.

Dave
 
thunter0512 said:
Is there some document or website which describes the straight 8 versus 8/s differences and the reasoning for not including the missing OPeRate instructions?
Click to expand...
Has anyone see one document that has all the instruction set differences between the PDP-8 models? I know I have seen portions in various places but don't remember seeing anything close to comprehensive.
 
thunter0512 said:
Is there some document or website which describes the straight 8 versus 8/s differences and the reasoning for not including the missing OPeRate instructions?
I am surprised that the serial nature of the CPU is the reason.
Click to expand...
I have never seen a DEC document detailing the differences. Doesn't mean there isn't one. But a long time ago I wrote a paper which included some of the differences as part of the comparisons of the different 8 processors. I am on the road so if I have that with me I will attach it, otherwise when I get home.

After thinking about this more it may not have been the serial nature, more likely the goal of making the cheapest possible PDP-8. The goal was to make a machine that they could sell at a profit for less than $10000.

And it is not that the OPeRate instructions are missing, it is that not all the combinations are supported. The different supported combinations is the major difference between all the CPU models.

Ok, I found the paper so it is attached. Looks like it could use another refresh as I know more now and I could include IOT timings and maybe talk more about EAE timings. I feel like it would be a good idea to add the PDP-5 to the comparisons too.
 

Attachments

  • PDP8-comparisons.txt
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djg said:
Has anyone see one document that has all the instruction set differences between the PDP-8 models? I know I have seen portions in various places but don't remember seeing anything close to comprehensive.
Click to expand...
I probably should have done the comprehensive list when I was doing my comparisons paper. I know I had a lot more notes but those are probably gone or so deeply buried as to be inaccessible.

DEC probably had this somewhere but I've never seen it.
 
daver2 said:
The PDP-8/S is largely based on transistorised flip-chips as opposed to integrated circuits.
Click to expand...
The only IC's in the S I can think of were in the Negibus to Teletype adapter that was housed in base of the Teletype. So strictly speaking not actually in the 8/S. The Flipchip modules used are normal R and S series with some G series in the core memory portion.

I have not looked at the S in detail, it seems like the AC, MA, MB, and PC have to be 12 bit registers. It is probably a one bit adder instead of a 12 bit, but how was this applied to the PC for increment?

That is all really a topic for another thread I suppose.
 
djg said:
Has anyone see one document that has all the instruction set differences between the PDP-8 models? I know I have seen portions in various places but don't remember seeing anything close to comprehensive.
Click to expand...
I think some of the better known ones were probably described in various Lasner rants.

I have a sort of bullet list that I've been working on embedded in the code for the version of SIMH that I'm working on which implements the model-specific stuff. There's a lot of it.

There are model-specific IOTs in the 600x range, the handling of non-existant memory is different, there are competing stack implementations, etc. etc.

Code: 
   Model        Limitations
   5            No IAC rotate, no CMA rotate, no EAE, 4K maximum, slower
                PC at 0000, Interrupts at 0001, no DMA (data break)
   8/S          No IAC rotate, no CMA rotate, no EAE, 8K maximum, 15x slower
   (straight) 8 No IAC rotate, IOT 6004 is special, no SWP, no SCL
                Nonexistent memory reference is special
   LINC-8       Like straight-8, but with LINC & LINC peripherals, 4K
   8/L          group 3 CLA is NOP, no EAE, 8K maximum, protect switch
                CDF/CIF to non-existant field is a NOP
                RAL RAR and RTL RTR, perform both AND results
   8/I          RAL RAR and RTL RTR, perform both AND results
   PDP-12       Same as 8/I, but with LINC & LINC peripherals
                IOT 6006 is special, DTLA conflicts with PUSHJ
   8/E/F/M      CAF, BSW, Omnibus I/O, MQL, MQA, SWP
                Odd semantics for RAL RAR, RTL RTR
                EAE option has mode B
   8/A          CAF, BSW, Omnibus I/O, PUSH/POP, 128K support
                Yet different semantics for RAL RAR, no EAE
                non-standard LPT
   VT78         CAF, BSW, Omnibus I/O, PUSH/POP
                RAL RAR and RTL RTR are NOPs
                Autoindex suppressed for current page accesses
                No restart from HLT, No DMA (data break)
   DECmates     CAF, BSW, R3L, Omnibus I/O, PUSH/POP
                RAL RAR is R3L, RTL RTR is NOP
                No EAE, EAE operations hang
                Incompatible second serial port (also model dependent)
                KSF, TSF, PSF implementation botched
                No restart from HLT in DECmate I
                Color graphics options
                Optional Z80 and 8086 coprocessor

   Most of these differences have to do with the treatment of IOT and OPR
   instructions.  There is a difference in the treatment of non-existant
   memory, and of current page indirection where the current page is page
   zero.  Quirks that are not fully implemented will be marked in the code
   with BUGBUG: or TODO: comments, based on the percieved serverity of the
   limitation imposed by their absence.
 
PDP-8 FOCAL seems to be able to identify what processor it is running on. Maybe a peek at the source code would give you some insight about detecting the diferences.
 
djg said:
Has anyone see one document that has all the instruction set differences between the PDP-8 models? I know I have seen portions in various places but don't remember seeing anything close to comprehensive.
Click to expand...
I've found the following Doug Jones page to be a handy reference. Refer to the "Compatibility" subtopic under each machine description.

It is quite specific for many machines but not for all. For example, the PDP-8/S description says: "The core of the PDP-8 instruction set is present, but there are a sufficient number of incompatibilities that, as with the PDP-5, many otherwise portable "family of 8" programs will not run on the PDP-8/S."

 
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