Asci Red ran 9,000 ppros in SMP, so limits are frungible. (Though even among my collogues who worked on it I can't get a consensus as to whether it was one distinct system or a beowulf cluster).
It was more tightly coupled than a Beowulf cluster, but it was still a message passing architecture; each compute node had its own memory, there was no global memory pool, and each compute node only had two CPUs.
I have one or two dual socket 7 boards that expected you to run multiple Pentium chips. It always made me wonder what bizarre hacks they were pulling off to make the multiprocessor 386/486/586 systems work because those were never expected to be used in the configuration and lacked many of the instructions to make it efficient.
386 multiprocessor systems and (I would wager) most 486 multi-CPU systems were proprietary asymmetric architectures that relied on cooperative message passing or other hacks (a late, more consumer-focused example of this would be the ill-fated BeBox with its multiple PPC603s), but some late 486 SMP systems complied with
the Intel Multiprocessor Specification, the first public version of which, 1.1, came out in 1994. MPS was originally implemented in the form of the 82489DX APIC, which worked with the 486 and early Pentium processors, while later "P54C" Pentium CPUs and all Pentium Pro CPUs have APICs integrated.
Anyway, all 90mhz and faster Pentium socket 5/7 CPUs technically have MPS-enabled onboard APICs, limited to a pair of CPUs. (My vague recollection is that the MPS standard as implemented on P6-family CPUs maxed out at 8, but it depended on the exact CPU type; IE, consumer CPUs like the PII/PIII could only do 2, Pentium Pro and Xeons could do up to 8 but, likewise, it may have depended on the CPU, some topped out at 4?) But obviously P5 SMP boards were pretty rare; none of Intel's mainstream consumer chipsets supported it so you had to use one of the older high-end chipsets that Intel mostly orphaned when the P6 came out, and they had compatability issues with OSes other than NT and whatnot. Strictly speaking more modern MPS compliant OSes like Linux *should* run on these, but I don't think anyone's tested it in over 20 years.
The fact that Intel put APICs in the P54Cs kind of implies Intel might have at least considered SMP as a consumer feature at some point, but I would guess they canned it because it was clear that NT just wasn't going to be mainstream anytime soon.