I thought the FreHD for the Tandy Model 3/4 was doing something like this, but it is not - it uses a one-way shift register for reads. For writes and read setup time, it halts the Model 3/4 CPU.
I suspected they probably did, the TRS-80 bus has a pretty easy to use WAIT line. Not having that facility on this bus is going to make this pretty tight on any MCU that doesn't specifically have a get-out-of-jail-free card like that input port on the PIC32.
(I am still very curious about that PIC's latency for reacting to the "this port was touched" events. On most machines likely to actually benefit from an XTA hard disk replacement if you can react to a value being read or written and update the register in something around the 1-microsecond ballpark that's probably enough?)
This does seem like a great option for a 5v, 40 pin micro. It is a little more costly than a 328, but not much so.
My big AVR project (currently on hold because of real life) started with a 328 and a GAL programmed to be an autoincrement counter for the LSB of a video address but going to the 324 and just using two ports for the MSB/LSB made life so much easier and more flexible. (I can do arbitrary strides through memory just by changing the increments, etc.)
I have a sleeve of these - I was thinking of designing a DMA circuit for old Tandy's.
I think for this project, if we are adding that much external memory, it is time to bite the bullet and use a CPLD.
As Chuck notes if you don't want voltage shifters there's not much in CPLD-land these days. A 74LVC245 might be *fine* even running bidirectionally because the PC bus should react to TTL level output highs, which are spec'ed at only 2.7 volts. Assuming it runs close to the rails like most CMOS devices I would think it should drive the bus adequately with a 3.3v VCC? You'll need 3.3v anyway for the SD card, so if the PIC will do the job it seems like a really attractive option.
Yeah, there are a lot of parts to implement.
I am *not* at all familiar with how fast DMA cycles are on the ISA bus compared to the 8088 cycles (I assume they replicate the T-state counts similarly), but assuming they *mostly* look like normal reads and writes in terms of latency and you can put together a bus interface that can respond to those with adequate latency then maybe the DMA isn't going to be that big of a deal? You'll need some flip-flop logic to assert DRQ and accept a DACK as the signal for the next byte to be supplied/processed, and at the end of the transfer (presumably in a case where you've transferred a full 512 byte sector?) you'll need to fire the interrupt pin. I don't know if that PIC32 will be able to handle that just through GPIO, but it is pretty fast in theory and if instead of using interrupts you switch to a tight polling loop during DMA transfers I'd think this might be surprisingly doable.