Eudimorphodon
Veteran Member
I am imagining a buffer circuit to sit between the 8250 and the bus to manage this
I'm not sure how that would add up; you would need a state machine sophisticated enough to actually do the fetch against the 8250's receive buffer, store it in a FIFO or ring buffer, and then somehow get the CPU up to speed after it's going through however many cycles that are in play without breaking software compatibility. (It'd have to generate a bunch of synthetic interrupts for each character in the FIFO?)
If the chip is socketed in the machine you could try replacing it with a 16550D, they're "pretty much" pin compatible; that will give you a 16 character deep FIFO. Downside is that the software you're using has to enable it, it's not "transparent".
It would be interesting to know *why* this machine might possibly need to generate an NMI to update the screen. I found a copy of the schematics online, but it's low res enough that I wasn't able to make out a lot of the labeling, especially on the keyboard controller sheet. The video hardware itself doesn't seem to point to any reason for needing an NMI, it looks like it's just a pair of 8K SRAMs for video RAM and otherwise mostly a slightly weird CGA implementation.