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Anyone really good with KiCAD PCB routing?

Chuck(G)

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I've got a board (6 by 4 inch) that I've laid out components on in PCBnew. (about 12 DIPs, connectors). Right now, I'm wondering if I should bother trying to make a regular PCB (with all the trace routing headaches) or do my usual wire-wrap implementation. The issue is for me that I'd like to share the design (assuming that it works) publicly (I'm at an age where I'm doing this for "fun"). It would never fly as a public project as a wire-wrap implementation. But I'm no genius at PCB layout--I've done a few and they work, but this one is a bit much for me and would take more time to get right than I'm willing to spend.

The project is a Pertec-tape interface to USB board with the bulk of the work being done by a STM32F407 MCU. If anyone is interested in tackling this one, I can forward the KiCAD files.
 

MattisLind

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Hello! USB to PERTEC sounds interesting. I have had such a project idea for some time which haven’t finished for various reasons..

Do you have a schematic already in KiCAD? The 407 is unobtainium when I checked a couple of weeks ago. Or do you plan to use one of those 407 based black boards? 12 dips sounds quite easy to route.

I am by no means a master of KiCAD but have routed a number of boards which has worked quite well. Both with through hole and SMD. most likely someone could do the job better but I was happy with the result.

You can forward the design files and I can have a look. No promises given yet though.
 

Chuck(G)

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I'm using the black 407 boards--I like them because they've got the clock battery, SD card and USB all on the same little board. I'll shoot you the schematics and the PCBnew layout.
 

whartung

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12 dips sounds quite easy to route.
Wow, really? I can't route 2 chips!

I'd love to see a video of someone doing some routing. Just to see how it's done by someone who knows what they're doing. Point out common problems and how they address them.
 

jlang

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I can describe how I route boards.
Placement is critical. I spend a lot of time placing parts to optimize the rats nest.
I spend a lot of time "gate swapping" and moving parts. The objective is to simplify the needed routes.
I may go back to the schematic several times to make changes, generate a new net and place it all over again.

For the actual routing I have a system.
I never auto route. I route power first. Insure I have fat traces for power. Move the bypass caps to minimize trace length.
Then i do signal routing. I'm very strict at this part. left-right on one layer. up-down on another later.
If need to change direction place a via and switch layer. no diagonal traces. (except .050 jogs to get between pins)
I haven't talked about ground yet. I use copper "pour" (fill) for ground both top and bottom layers.
That's the reason for the strict horizontal vertical signal routing. You are almost guaranteed to have a path for the pour.
I then examine the length of the ground paths between the bypass caps and the chip grounds and punch in some stitch vias
if necessary.

I would point out I'm retired and doing hobby projects so not a lot of need for stripline and matched differential signals.

joe
 

Chuck(G)

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I can describe how I route boards.
Placement is critical. I spend a lot of time placing parts to optimize the rats nest.

Sure, I work with 2 displays--one has the eeSchema display; the other the PCBnew display. The thing is that if I were WW this for myself, I'd organize parts to make sense logically and then proceed from there. Case in point--Pertec tape interface is spread across two 50-pin headers. There's no logical ordering of the pins; for example, read data is spread across both connectors in no particular order. The drive-to-host signals are terminated by 220/330 ohm SIP networks; I spent most of a day, playing with the ordering to minimize track crossings. If I were wire-wrapping, I'd organize the 220/330 pins in logical order; for example, Data bits 7654321 on a single SIP and take it from there, for example. It makes sense to the eye and the mind.

I could see that PCB layout would take much of a week's work to get just right. Since this is a prototype, there's always the possibility that it may need ripping up nets and redoing them. I can work from a WW prototype very easily--getting it all wired up shouldn't take me more than 2 days. I've got lots of WW supplies and am very fast with a gun. But the VCF community would never stand for something like this. FWIW, signals are perhaps 1 MHz tops; all the fast logic is already done on the MCU mezzanine. I usually do my work starting with a blank single-copper FR4 PCB; the copper serves as a continuous ground plane.
 

jlang

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I had the good fortune some decades ago to walk into a local surplus shop and see a pile of Augat wirewrap panels.
The really nice ones. Ground and VCC planes. Full of WW pins. I cleaned out the shelf. (wife not so happy)
I've lost count of the number of WW projects I've done.
I didn't know the VCF community was anti-wirewrap.

joe
 

Chuck(G)

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It's not the VCF in particular; it's more like the general community of the younger folks who are unfamiliar with the technology. Early simulations of MPUs were done in wirewrap, as were complete projects. I would be surprised if the original Apple I went straight to PCB rather than wirewrap. A lot of mainframe backplanes were WW also. Stuff I did 30 years ago still works. For prototyping, a design error is fairly easy to correct. ECL, for example, could be done with twisted pair for the differential signals.

I'll agree that if you're dealing with high-frequency signals, wire-wrap might not be the right tool for the job.
 

Dwight Elvey

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I don't like using KiCad's package for TTL IC and such. It wants to make individual gates in the schematic that do not layout well. I make all the ICs as packages with the pins as they would be for the actual package. I've not figured how to stop KiCad from using what it thinks you want to use. I've had to use alternate names for things like 7400 and such. How is one suppose to know which pins you want to use before considering the layout??
This way, one can layout the schematic similar to how the IC will be placed on an actual board. This helps to reduce routing congestion when working on a tight board.
When bringing components in, build your board off to the side and not centered. Spread the parts around first to get a feel for placement.
Place major parts first and watch for congestion. If working with 2 layer boards try to keep wires left to right or top to bottom. Also remember feedthrus are space hogs so take advantage of IC pins for these whenever possible. ( I mean expensive in space ). Avoid too many 45 degree runs and also stay away from right angles on a single side unless it is one of the last traces you are putting down. If you don't follow this rule, you'll reduce later routing options. Remember to keep runs top to bottom and right to left as straight as possible.
I've only done 3 boards with KiCad but have some experience with older cad systems.
Dwight
 

Chuck(G)

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You can always add a unified TTL package to your symbol library. There are times when I want to split, say, a 74LS74 into two parts with one part on one page and the other on another page. Makes sense, as the two parts share only power and otherwise don't interact.
Even wire-wrapping, the PCBnew rat's nest display is good for picking out very long wires that could be made shorter.

There are other times, when, say constructing two RS flip-flops from a 74LS00 that you want it all in a nice single package.
 
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Dwight Elvey

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Anyway, you can make your own parts and you can take advantage of doing that to your hearts desire. It is just that you can't use the name 7400. At least I've not found a way.
Dwight
 

Eudimorphodon

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Even wire-wrapping, the PCBnew rat's nest display is good for picking out very long wires that could be made shorter.

It's also good for telling you that maybe you should rewrite your first draft of PLD code to rearrange the pin order so it actually makes sense.
 

Chuck(G)

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What PLD? This design is all jelly-bean TTL; through-hole at that. Why? Because people are afraid of programmable devices and surface-mount stuff. I'm trying to do an open-source design that few will have problems with. If it were just for myself, I'd go with CPLDs and wire-wrap.
 

Eudimorphodon

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What PLD? This design is all jelly-bean TTL; through-hole at that. Why? Because people are afraid of programmable devices and surface-mount stuff.

In my case PLD almost always means "GAL", generally in a DIP form factor, so functionally I guess I'm working somewhere in the no-man's zone between the "all TTL forever" and "just slap an FPGA on it" schools of thought. But my comment might also apply if you're using arbitrary GPIO pins on a microcontroller that could be rearranged.
 

Chuck(G)

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Not arbitrary, but interface brought out to headers to be connected to the MCU board of your choice. The goal is keeping it real for the long haul. It wasn't that long ago (at least in my mind) that the 8051 was the most popular MCU.

Yes, I could have reduced the number of packages by adding some programmable logic. But this stuff is all 5V, and ancient 5V GALs/CPLDs are getting pretty scarce new.

I should mention that I did do a version with almost all of the board logic stuck in a single Xilinx XC95108 84 pin 5V PLCC. I can't see how that would appeal to anyone, given that the only source seems to be the gray market. But my hellbox has a few new ones...
 
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Chuck(G)

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For jollies, here's the interface of the CPLD version to the MCU:

Code:
//      The following are lines between the CPLD interface to the host CPU.
//
//      AD = 8 bit address/data bidirectional bus
//      RD = Pulsed low for read internal register
//      WR = Pulsed low for write internal register
//      CSEL = chip select (active low)
//      R = 2 bit register number.
//      CLR = pulsed low to clear internal registers.
//      TBE = low when transit buffer empty
//      RBF = low when receive buffer full
//      IRQ = end-of-operation interrupt request

(Yes, I'm old and Verilog is my HDL of choice)
 

Eudimorphodon

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Just to be clear, I wasn't suggesting there was anything wrong with your design, I was just chiming on the general topic of "strategies for making PCBs easier to lay out". I'm a little worried you're taking it the wrong way; the comment was strictly meant in the abstract and along the same lines as, say, rearranging your schematic to use different units in multi-unit TTL parts if changing the pin order optimizes the design.

Yes, I could have reduced the number of packages by adding some programmable logic. But this stuff is all 5V, and ancient 5V GALs/CPLDs are getting pretty scarce new.

FWIW, Microchip/Amtel is still churning out new ATF22V10s and 16V8s. They're also pretty beginner friendly because they can be readily programmed by those cheap TL866 programmers. That's why I use them. Not saying anyone else should.

(* EDIT: Okay, normally they're readily available, but, man, apparently the chip shortage has come for my GALs. The inventory at both Digikey and Mouser is *seriously* picked over, and the anticipated delivery dates... seriously?)
 

Chuck(G)

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Oh no, I'm not taking it the wrong way. In a way, I'm lamenting the demise of 5V programmable logic. Yes, I know there's still 5V-tolerant logic, but it's not the same thing, but maybe I should consider it. On the other hand, I can build my interface using the CPLD, publish the Verilog and leave it to someone else to implement using a different device. Decisions, decisions...
 
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