• Please review our updated Terms and Rules here

Commodore 3016 scrambled screen

>>> Check the simple things first, oddly the jumpers on the two jumper blocks are incorrect for a 32k PET. On the 6 way block jumper D should be closed and on the 10 way block jumper k should be closed. You can solder those cut jumpers back together, the rest look correct.

@Hugo Holden

It is my assertion that links 'D' and 'K' are not actually used. Or (at least) I don't see them described on the schematics...

Dave
 
daver2 said:
>>> Check the simple things first, oddly the jumpers on the two jumper blocks are incorrect for a 32k PET. On the 6 way block jumper D should be closed and on the 10 way block jumper k should be closed. You can solder those cut jumpers back together, the rest look correct.

@Hugo Holden

It is my assertion that links 'D' and 'K' are not actually used. Or (at least) I don't see them described on the schematics...

Dave
Click to expand...
Probably right, since it must have been working in the past with those links cut, it is just that I noticed it didn't match what was in the manual for the jumpers for the 32k PET. I did not look at the schematic or the physical board to check where, if anywhere, those jumpers went.
 
One good way to help protect the CPU socket, is to have the final item that plugs into it made from a typical dual wipe IC socket, the reason is these sockets have thin flat pins that are almost idental in geometry to an actual IC pin. If anything bigger is inserted into the socket it stretches the socket claws and they lose spring force and are not as good when the CPU is put back into the socket later.

I built a somewhat more elaborate NOP generator with DIP switches to switch the NOP condition on or off, and a ROM used as an address range decoder to provide signals that I could use for scope synchronization to examine events that occurred in that address range only with the other scope channel, plus convenient test points for the CPU. On the rear of this board is a dual wipe IC socket that plugs into the PET's CPU socket.
 

Attachments

  • NOP.jpg
    NOP.jpg
    665.9 KB · Views: 6
Last edited:
Created NOP generator. Tested pins on CPU.
Freqency is as you mentioned. 250-125-62.5 etc.
Also checked in and out on C3 en B3. Seems also ok.
Edit: I seems like pin 25(AB15) on cpu is 'flipping' also on B3 input 11 and output 9
Al others are stable.
 
Last edited:
Hugo Holden said:
One good way to help protect the CPU socket, is to have the final item that plugs into it made from a typical dual wipe IC socket, the reason is these sockets have thin flat pins that are almost idental in geometry to an actual IC pin. If anything bigger is inserted into the socket it stretches the socket claws and they lose spring force and are not as good when the CPU is put back into the socket later.

I built a somewhat more elaborate NOP generator with DIP switches to switch the NOP condition on or off, and a ROM used as an address range decoder to provide signals that I could use for scope synchronization to examine events that occurred in that address range only with the other scope channel, plus convenient test points for the CPU. On the rear of this board is a dual wipe IC socket that plugs into the PET's CPU socket.
Click to expand...
That looks very nice. I wonder if there is any gerber PCB available to build it correctly.
 
Excellent. So, the next little device to test is D2.

This is a 4 to 16 address decoder. It splits the 64K address space up into 16 blocks of 4K.

The outputs are all active LOW.

What you should observe is a LOW pulse on each output for 1/16 of the total cycle time. High for 15/16 of the time and low for 1/16 of the time.

If you have a dual channel oscilloscope, you should be able to see the one pulse (say on pin 16) occurring before the next pulse (say on pin 17).

The outputs are numbered /0 through to /15.

Does this make sense?

Dave
 
daver2 said:
Excellent. So, the next little device to test is D2.

This is a 4 to 16 address decoder. It splits the 64K address space up into 16 blocks of 4K.

The outputs are all active LOW.

What you should observe is a LOW pulse on each output for 1/16 of the total cycle time. High for 15/16 of the time and low for 1/16 of the time.

If you have a dual channel oscilloscope, you should be able to see the one pulse (say on pin 16) occurring before the next pulse (say on pin 17).

The outputs are numbered /0 through to /15.

Does this make sense?

Dave
Click to expand...
Did you also read my edit in my comment?.

I seems like pin 25(AB15) on cpu is 'flipping' also on B3 input 11 and output 9

I that ok?
 
I suspect it is a trigger issue with your oscilloscope and/or you are running the timebase too quickly.

Dave
 
Ok, so if D2 is happy, this confirms the AB15 signal as good...

Just about to start our street party now, so I will be back after a few drinks... In which case, ignore everything I post!

Dave
 
OK, I am off to Church in a few minutes (doing the sound mix on our second service. My son is doing our first service).

We can continue after lunch (once I have tided away the remaining stuff from the Coronation Party we had yesterday that is...

Dave
 
TheMatrix said:
That looks very nice. I wonder if there is any gerber PCB available to build it correctly.
Click to expand...
I am sorry but I don't have Gerbers. I build it on a proto board from the schematic I designed.

When I design a pcb for it, I send it to the pcb maker as a .jpg image and they convert it into a Gerber at their end and make the pcb.

( I'm beginning to wonder now, if there is an AI out there, than can convert my .jpg pcb images into a Gerber).
 
Last edited:
Hugo Holden said:
I am sorry but I don't have Gerbers. I build it on a proto board from the schematic I designed.

When I design a pcb for it, I send it to the pcb maker as a .jpg image and they convert it into a Gerber at their end and make the pcb.

( I'm beginning to wonder now, if there is an AI out there, than can convert my .jpg pcb images into a Gerber).
Click to expand...
I found your topic.
Looks very nice and easy to build with your example.
 
daver2 said:
OK, I am off to Church in a few minutes (doing the sound mix on our second service. My son is doing our first service).

We can continue after lunch (once I have tided away the remaining stuff from the Coronation Party we had yesterday that is...

Dave
Click to expand...
Do you have more tips what to test now? ;):)
 
Got distracted by an APL port that is driving me nuts!

Ok, so you have the NOP generator in and ticking away. Yes?

Dave
 
Here we go...

CPU pin 34 (R/W) should be HIGH. Only ever READ with the NOP generator.

Follow this signal through the logic gates:

A10/4 HIGH.
A3/12 LOW.
A3/8 HIGH.

CPU pin 39 (Phi2) should be a 1 MHz clock.

Follow this signal through the logic gates:

A10/8 1 MHz.
A10/2 1 MHz.

E9 and E10 pins 1 and 19 should both be pulsing.

Check pin 20 of all of the ROMs. They should be pulsing.

Check that I10 and I11 pin 1 are pulsing.

Check that I10 and I11 pin 19 are HIGH.

Check that I2 pin 3 is HIGH.

I2/4 is pulsing.

I2/15 is pulsing.

J2/15 is pulsing.

I2 pins 5, 7, 6, 12, 11, 10 and 13 are pulsing.

E7 and E8 pin 1 are pulsing.

E7 and E8 pin 19 are HIGH.

Check all of the signals identified as RDn and BDn on I10 and I11.

Check all of the signals identified as SDn and BDn on E7 and E8.

Check all of the signals identified as BDn and Dn on E9 and E10.

All signals should be either TTL high, TTL low or pulsing between TTL high and TTL low.

We are looking for nice (ish) signals. Unfortunately, vintage computers tend to have some horrid-looking signals at times, but they should definitely avoid the 1.0 to 2.5 Volt area. This would potentially indicate bus contention.

I am sure I have made the odd typo. above...

Dave
 
You must log in or register to reply here.
Back
Top