TheMatrix
Experienced Member
Checked most things. looks ok.Here we go...
CPU pin 34 (R/W) should be HIGH. Only ever READ with the NOP generator.
Follow this signal through the logic gates:
A10/4 HIGH.
A3/12 LOW.
A3/8 HIGH.
CPU pin 39 (Phi2) should be a 1 MHz clock.
Follow this signal through the logic gates:
A10/8 1 MHz.
A10/2 1 MHz.
E9 and E10 pins 1 and 19 should both be pulsing.
Check pin 20 of all of the ROMs. They should be pulsing.
Check that I10 and I11 pin 1 are pulsing.
Check that I10 and I11 pin 19 are HIGH.
Check that I2 pin 3 is HIGH.
I2/4 is pulsing.
I2/15 is pulsing.
J2/15 is pulsing.
I2 pins 5, 7, 6, 12, 11, 10 and 13 are pulsing.
E7 and E8 pin 1 are pulsing.
E7 and E8 pin 19 are HIGH.
Check all of the signals identified as RDn and BDn on I10 and I11.
Check all of the signals identified as SDn and BDn on E7 and E8.
Check all of the signals identified as BDn and Dn on E9 and E10.
All signals should be either TTL high, TTL low or pulsing between TTL high and TTL low.
We are looking for nice (ish) signals. Unfortunately, vintage computers tend to have some horrid-looking signals at times, but they should definitely avoid the 1.0 to 2.5 Volt area. This would potentially indicate bus contention.
I am sure I have made the odd typo. above...
Dave
Now last part. But what dou you mean by this?:
Check all of the signals identified as RDn and BDn on I10 and I11.
Check all of the signals identified as SDn and BDn on E7 and E8.
Check all of the signals identified as BDn and Dn on E9 and E10.
And typo here?
A10/4 HIGH.
A3/12 LOW.
A3/8 HIGH.
CPU pin 39 (Phi2) should be a 1 MHz clock.
Follow this signal through the logic gates:
A10/8 1 MHz.
A10/2 1 MHz.