C64 IN PET S' CASE

[Hugo Holden]

hi guys, @daver2 @Hugo Holden I have completed the new drawing and I would like you to check if everything is ok.
I drew without tags because I noticed you don't like them.
please report any errors because I'm learning, thanks.
If it helps but I discovered an error with the monitor connector on the previous PCB.

Hi Antony,

There have been so many changes to the wiring, I have lost track of what is connected where and on the prototype board that Desperado is trying to fix.

The main thing at the moment, is to go back to basics and how it is supposed to work. See attached timing diagram.

One improvement I think would be to trigger monostable IC2A from pin 8 of the 74LS10, rather than the collector of Q1 directly, because it is a better compatible TTL rise & fall time at that point after being squared up by the two gates and monos can be tricky with triggering.

Ideally the monostable IC3B that generates the the H drive pulse should not be adjustable, and simply set close to 23uS with a fixed resistor and timing capacitor.

Likewise IC3A for the vertical pulse is better settled on a fixed value close enough to 1.26mS

The one H line delay (63uS) needs to be adjustable to center the video text, and the 10uS H blanking pulse adjustable in case the 10uS wasn't quite long enough to blank the H retrace in the VDU.

I haven't draw in the capacitor values or preset values, but the capacitors were already settled on and the presets chosen.

So perhaps if you could re-draw up the new schematic to conform to this basic arrangement and check the timing values from the IC data sheets, it should work.

 

[Hugo Holden]

I have re-attached the diagram with some information about the scan time and retrace going on inside the VDU.

There is only one thing about it that bothered me, and it is part of the original design too. But in the original application the issue would not affect or cause trouble the more usual type of VDU that had its own internal oscillator and AFC system as this smooths out any glitches in the H sync.

Unfortunately the 9" PET VDU does not have this system and relies on a clean & perfectly regular H drive signal uninterrupted by anything, as this controls the H output transistor.

Though, before the 1 H line delay was put in to center the text, it didn't seem to trouble Desperado's 9" VDU much and there "appeared" to be no issue. Only after the 1 line delay was put in did the buzz sometimes occur when he went to center the text.

I think probably what is happening with the buzz at times, is that the vertical sync pulse within in the composite sync pulse feeding monostable 2A is likely causing triggering or pausing of the monostable 2A and thereby putting a "60Hz glitch" into the H drive pulse, hence the buzz. It is easy to fix it, but Desperado was running out of monostables on his highly modified pcb.

To make sure that the H sync pulse feeding monostable 2A is perfectly clean and free from any glitches cause by either the V sync component in it ( or any equalizing pulses if they happened to be there too) , the attached circuit works and on the basic diagram it would go in series where the circuit is cut at the Red X. It will mean having to add another IC. The output could also come from pin 13 (Q) output) of this circuit rather than /Q, it shouldn't matter what way up the regenerated H sync is as it is a fairly narrow 3uS pulse and will trigger IC2A in both cases.

 

[Desperado]

Thanks Hugo, do you recommend redoing the whole PCB then?

 

[daver2]

Hugo has very kindly put the waveforms on his drawing that you should observe on your oscilloscope, and their timing relationship to each other.

Is this what you get?

Dave

 

[Desperado]

and their timing relationship to each other.

how can i do to see this?

 

[daver2]

We were already doing it, but we are not seeing on your oscilloscope screen what we were last time...

We were using IC2/2 as the trigger (on channel 2) which corresponds to Hugo's grey trace, and then use our channel 1 to look at the other points...

Dave

 

[Desperado]

Need i leave CH2 on IC2 pin 2 ?

 

[daver2]

As I have just posted, yes - this is our trigger/reference point in time.

Then use channel 1 to look at the IC pins associated with A, B and C.

Dave

 

[antony]

well, @Hugo Holden I have to add a 74ls221, as you drew. the circuit becomes more and more complex and interesting. As soon as I make the new drawing I'll update you. Thank you

 

[antony]

@Desperado hai capito? come ti dicevo le interferenze sono generete dal circuito dei monostabili, sul 12" c'è un circuito di filtraggio che aggira il problema ma sul 9" questo non c'è.
l'unico modo è aggiungerlo sul pcb, utilizzando un secondo 74LS221 in modo da ripulire il segnale da inneschi involontari dei due monostabili a 60hz che si sovrappongono al segnale , interferenza che manda in errore i sincronismi del monitor. Daver2 sta cercando di farteli visualizzare con l'oscilloscopio questo sarà la conferma della teoria, nel frattempo devo aggiornare il circuito. buon lavoro ragazzo facci vedere cosa sai fare!

 

[Hugo Holden]

Thanks Hugo, do you recommend redoing the whole PCB then?

Well, it would not be a bad idea to try to get the entire circuit working first, make sure it is good, before sending it to the pcb maker, or it might still need a modification and create a mess.

Most people wire things up on prototype pcbs, get that working, then get the pcb made after that, to avoid wasting money on pcb's that don't work out well. Though for simple cases a simulator works, but in this case there are a few unknowns, for example, exactly what the composite video signal looks like from the computer, in the vertical block area, where the H & V syncs are mixed together.

 

[daver2]

@Desperado,

Have you given up with the oscilloscope traces I was asking for?

Dave

 

[Desperado]

@Desperado,

Have you given up with the oscilloscope traces I was asking for?

Dave

yes Dave, I'm waiting for Antony to finish the schematic and then produce the new pcb. It has now become difficult to make other changes or measures on this. I am desperate!

 

[daver2]

Ok.

Well, measuring signals is just measuring the pins of the ICs, using the oscilloscope correctly and twiddling the appropriate potentiometers.

In my opinion, you are better doing that before the new PCB is made...

Dave

 

[antony]

@Hugo Holden hi, please check if it is correct thanks

 

[Desperado]

Thanks so much DOC Antony!

 

[Hugo Holden]

@Hugo Holden hi, please check if it is correct thanks

A diagram like that is much harder to check for errors and looks more like a schematic for a refrigerator. It is easier when the IC's like the 74LS10 are drawn as gates with numbered pins, and each monostable, inside each IC, is drawn as a block with its timing resistor/s and capacitors, so it is much clearer to see that everything is wired the way it should be. I would have to re-draw it, in conventional schematic form, to check it properly.

 

[Desperado]

Hello guys!! Please what can i do now?? time to white flag for this project?

 

[daver2]

I thought you were going to construct a new PCB - so we are waiting for you...

The thing that we don't like about the redrawn schematic is that it has been completely redrawn from the original - so it will take us a lot of time to check it ourselves...

Dave

 

[antony]

@Hugo Holden , @daver2 , that's a prewiev of pcb workinprogress