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Commodore pet 2001-8 no video from logic board

C7 pins 2, 3 and 12.

Pins 2 and 3 should be the logical inverse of each other.

I think pin 12 should be 2 MHz.

I am looking for both a healthy voltage swing and what the frequency is.

Dave
 
daver2 said:
C7 pins 2, 3 and 12.

Pins 2 and 3 should be the logical inverse of each other.

I think pin 12 should be 2 MHz.

I am looking for both a healthy voltage swing and what the frequency is.

Dave
Click to expand...
Yes I remember now. Strange as I remember replying. Well a part of me does.
C7
Pic 1 Pin 2 moved up 4 squares
Pic 2 Pin 3 moves a few millimetres
Pic 3 pin 12 at 0.5us
 

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Nivag Swerdna said:
Replace A1 (74LS93)
Click to expand...
I like this theory too. If the counter was working, I think you would see recognizable characters on the screen. But with the counter not going through all eight lines per character, the latches/counters at the bottom would go through the screen memory addresses faster than they should thus shortening the "video on" state.
 
C7 is not toggling the output despite a clock being fed into it.

Is it possible you have the timebase too fast to see anything on pins 2 or 3?

Dave
 
daver2 said:
C7 is not toggling the output despite a clock being fed into it.

Is it possible you have the timebase too fast to see anything on pins 2 or 3?

Dave
Click to expand...
Pic1 Pin 2 0.5us
Pic 2 pin 3 0.5us
If i swing the other way I only get a line
 

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We all missed a clue in the recording of the V drive pulse.

Well it was spotted that this was running x4 faster than it should be out of the state machine. We did not check what will be the spacing between the pulses inside the groups of 4 narrow clock pulses clocking the state machine (assuming the state machine is normal which we think it is).

The spacing between the narrow clock pulses should be about 1.28mS (see the diagram I attached previously).

But, if you look at the scope recording at the time the signal is low, these are in fact only about a quarter of that, at around about 0.29mS as best I could measure from the scope photo.

This means that during that group of 4 pulses, IC C7 is being allowed to be clocked (by controlling its J input, which has to be high to enable it to toggle) x4 as frequently as it should be. C7 has a 2MHz actual clock pulse, suggesting that the narrow clock pulses in this PET , for the state machine are probably about 500nS wide. The control signal for the J input signal comes via C6 pin 11. Both of C6's inputs and its output need checking on the scope, on channel on the other and the other channel checking the two inputs separately. And one of the inputs to C6 is the result of the decoding performed by E8 , via D8.

So this is all leading in the same direction, that the most probable issue is a decoding error, say if one of E8's inputs had gone internally open circuit and had assumed a high logic state in the IC, but all the other mentioned gates need checking on the scope too, with one channel on the output and the other probing the input, to verify they are behaving according to their truth table.
 
Nivag Swerdna said:
@Hugo that is where I was headed... but I am now tempted to believe B1 p8 is clocking x4 due to A1 being broken... I guess we find out tomorrow...
Click to expand...


That makes sense. The output signal from B1 is called the /RELOAD signal on other PET schematics and it determines the time everything in the vertical system recycles.

A1 is set up as a divide by 8 (overflowing) ripple counter with one of the 8 states 111 decoded by B1 pin 9, 12 & 10.

It would pay to check the clock frequency fed to A1 on its pin 1. If that is normal then:

Since the pulses out of B1 have not disappeared, but are clocking x 4 faster, the first flip flop used in the '93 counter A1 ( input pin 1 output pin 9) must be working. Lets postulate two scenarios to work out which of the two IC's is defective:

1) If the outputs of the next two flip flops in A1 are stuck high, pin 8 and pin 11 of A1 stuck high, then the three bits would decoded by a working B1 and become a divide by two, instead of a divide by 8, making B1's output pulse on pin 8 4 x faster. .......alternatively.....

2) If we state that A1 is normal, then to get this effect, if it were an IC failure as the cause, it would be required that two of the input pins 12 & 9 had gone open circuit inside the IC B1 and assumed a high logic state and effectively B1 was ignoring these inputs. Seems a little less plausible, but it is still possible. I had a 74 IC once where two of its pins did go O/C and assume a high state internally.

In light of the above it certainly seems that A1 has likely failed and all we need to do is suggest scoping pin 8 & 11 of A1, no pulses & stuck high then A1 has failed. Normal looking pulses on 8 & 11 of A1 then B1 likely failed......but there is a big trap to fall into:

We could make a third postulate and say that both of these IC's are perfectly good, then what ?

The effect could also be caused if the tracks leading from A1 pin 8 to B1 pin 12 and the track from A1 pin 11 to B1 pin 9, were for some reason, open circuit.
 
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Hugo Holden said:
That makes sense. The output signal from B1 is called the /RELOAD signal on other PET schematics and it determines the time everything in the vertical system recycles.

A1 is set up as a divide by 8 (overflowing) ripple counter with one of the 8 states 111 decoded by B1 pin 9, 12 & 10.

It would pay to check the clock frequency fed to A1 on its pin 1. If that is normal then:

Since the pulses out of B1 have not disappeared, but are clocking x 4 faster, the first flip flop used in the '93 counter A1 ( input pin 1 output pin 9) must be working. Lets postulate two scenarios to work out which of the two IC's is defective:

1) If the outputs of the next two flip flops in A1 are stuck high, pin 8 and pin 11 of A1 stuck high, then the three bits would decoded by a working B1 and become a divide by two, instead of a divide by 8, making B1's output pulse on pin 8 4 x faster. .......alternatively.....

2) If we state that A1 is normal, then to get this effect, if it were an IC failure as the cause, it would be required that two of the input pins 12 & 9 had gone open circuit inside the IC B1 and assumed a high logic state and effectively B1 was ignoring these inputs. Seems a little less plausible, but it is still possible. I had a 74 IC once where two of its pins did go O/C and assume a high state internally.

In light of the above it certainly seems that A1 has likely failed and all we need to do is suggest scoping pin 8 & 11 of A1, no pulses & stuck high then A1 has failed. Normal looking pulses on 8 & 11 of A1 then B1 likely failed......but there is a big trap to fall into:

We could make a third postulate and say that both of these IC's are perfectly good, then what ?

The effect could also be caused if the tracks leading from A1 pin 8 to B1 pin 12 and the track from A1 pin 11 to B1 pin 9, were for some reason, open circuit.
Click to expand...
We have traces for A1 in the last few posts, see what you think ;)
 
Just checked connections between A1 B1
A1 pin 11 to b1 pin 9
A1 pin 8 to b1 pin 12
A1 pin 9 to b1 pin 10
A1 pin 1 to b1 pin 13
All ok
 
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